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標題: 90奈米射頻場效電晶體特性分析及研究
Study and Analysis on 90 nm Radio-Frequency MOS Transistor
作者: 陳宏榮
Chen, Hung-Jung
關鍵字: MOS transistor;金氧半場效電晶體;Multi-finger type;Threshold voltage;Cut-off frequency;Maximum oscillation frequency;Unconditional stability frequency;多指型;臨界電壓;截止頻率;最大震盪頻率;無條件穩定頻率
出版社: 電機工程學系所
引用: [1] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver,” IEEE J. Solid-State Circuits, Vol. 31, No. 7, pp. 880-889, 1996. [2] C. C. Enz and E. A. Vittoz, “An analytical MOS Transistor model valid in all region of operation and dedicated to low voltage and low-current applications,” Analog Integrated Circuit and Signal Process, Vol. 8, pp. 83-114, 1995. [3] Eyad A.-A. and T. Manku, “A small-signal MOSFET model for radio frequency IC applications,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, pp. 437-447, May 1997. [4] Y. Cheng and M. Matloubian, “Frequency-dependent resistive and capacitive components in RF MOSFETs,” IEEE Electron Device Letters, Vol. 22, pp. 333-335, July 2001. [5] M. Berroth and R. Bosch, “Broad-band determination of the FET small-signal equivalent circuit,” IEEE Transactions on Microwave Theoryand Techniques, Vol. 38, pp. 891-895, July 1990. [6] G. Dambrine et al., “A new method for determining the FET small-signal equivalent circuit” IEEE Transactions on Microwave Theory and Techniques, Vol. 36, pp. 1151-1159, July 1988 [7] 施敏著, 黃調元譯, 半導體元件物理與製作技術第二版, 國立交通大學出版社, 2002. [8] K. Iniewski, “A new method for the work-function difference determination using buried-channel MOS transistors,” IEEE Transactions on Electron Devices, Vol. 36, pp. 152-153, January 1989. [9] T. Yamashita, Y. Nishida, K. Eikyu, H. Oda, Y. Inoue, and K. Shibahara, “Threshold voltage modulation using implantation into substrate for Ni fully silicided Gate/High-k NMOS,” IEEE Electron Device Letters, Vol. 29, pp. 1163-1166, October 2008. [10] Asenov et al., “Simple model for threshold voltage of a nonuniformly doped short-channel MOS transistor,” IEEE Electronics Letters 27th, Vol.18, pp. 481-483, May 1982. [11] X. Zhou, K. Y. Lim, and D. Lim, “A new critical-current at linear-threshold method for direct extraction of deep-submicron MOSFET effective channel length,” IEEE Transactions on Electron Devices, Vol. 46, pp. 1492-1494, July 1999. [12] X. Zhou, K. Y. Lim, and D. Lim, “A new ‘A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling’,” IEEE Transactions on Electron Devices, Vol. 46, pp. 807-809, April 1999. [13] C.-Y. Lu and James A. Cooper Jr., “A new constant-current technique for MOSFET parameter extraction,” IEEE Solid-State Electronics, Vol. 49, pp. 351–356, 2005. [14] J. J. Liou, A. Ortiz-Conde, and F. G. Sanchez, “Extraction of the threshold voltage of MOSFETs: an overview,” IEEE Electron Devices, pp. 31 - 38, Auguest 1997. [15] T. Ytterdal et al., “Device modeling for analog and RF CMOS circuit design,” John Wiley & Sons, 2003. [16] A. M. Mangan, S. P. Voinigescu, and M.-T. Yang, M. Tazlauanu, “De-embedding transmission line measurements for accurate modeling of IC designs,” IEEE Transactions on Electron Devices, Vol. 53, pp. 235-241, February 2006. [17] H. Cho and D. E. Burk, “A three-step method for the de-embedding of high-frequency S-parameter measurements,” IEEE Transactions on Electron Devices, Vol. 38. pp. 1371-1375, June 1991. [18] T. E. Kolding, “A four-step method for de-embedding gigahertz on-wafer CMOS measurements,” IEEE Transactions on Electron Devices, Vol. 47, pp. 734-740, April 2000. [19] B. Razavi, R.-H. Yan, and K. F. Lee, “Impact of distributed gate resistance on the performance of MOS devices,” IEEE Transactionson circuits and systems, Vol. 41, pp. 750-754, November 1994. [20] I. Kwon, M. Je, K. Lee, and H. Shin, “A simple and analytical parameter-extraction method of a microwave MOSFET,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, pp. 1503-1509, June 2002. [21] C. C. Enz and Y. Cheng, “MOS transistor modeling for RF IC design,” IEEE Transactions on Solid-State Circuits, Vol. 35, pp. 186-201,February 2000. [22] S. H.-M. Jen, C. C. Enz, D. R. Pehlke, M. Schroter, and B. J. Sheu, “Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz,” IEEE Transactions on Electron Devices, Vol. 46, pp. 2217-2227, November 1999. [23] J. Han, M. Je, and H. Shin, “A simple and accurate method for extracting substrate resistance of RF MOSFETs,” IEEE Electron Device Letters, Vol. 23, pp. 434-436, July 2002. [24] Y. Cheng, M. J. Deen, and C.-H. Chen, “MOSFET modeling for RF IC design,” IEEE Transactions on Electron Devices, Vol. 52, pp. 1286-1303, July 2005. [25] Yu-Cheng Teng, “UMC 90nm logic ang mixed-mode 1P9M low-K process design support manual,” UMC Cop., April 2009. [26] Y.-S. Lin, “An analysis of small-signal source-body resistance effect on RF MOSFETs for low-cost system-on-Chip (SoC) applications,” IEEE Transactions on Electron Devices, Vol. 52, pp. 1442-1451, July 2005. [27] C. C. Enz, “An MOS transistor model for RF IC design valid in all regions of operation,” IEEE Transactions on Microwave Theory and Techniques, Vol. 50, pp. 342-359, January 2002. [28] S. Lee, H. K. Yu, C. S. Kim, J. G. Koo, and K. S. Nam “A novel approach to extracting small-signal model parameters of silicon MOSFET''s,” IEEE Microwave and Guided Wave Letters, Vol. 7, pp. 75-77, March 1997. [29] T. Manku, “Microwave CMOS-Device physics and design,” IEEE J. Solid-State Circuits, Vol. 34, pp. 277-285, March 1999. [30] David and Pozar, “Microwave Engineering,” John Wiley & Sons, 2005. [31] T. H. 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This thesis includes two parts. In the first part, the DC characteristic of multi-finger type MOS transistor has been discussed with different layout geometries. Measurement shows that the high gate voltage and low drain voltage have the specific transconductance value. This value could be used to derive the threshold voltage. The semiconductor physics was used to explain the optimal DC bias voltage.

In the second part, the RF characteristic has been analyzed based on previous DC bias. Investigation on the parasitic value in small-signal model has been paid in this thesis. Moreover, the parasitic effect is characterized with different layout parameters. The substrate resistance is investigated in this work. Adopting the concept of power flow, three critical parameters such as cut-off frequency (ft), unconditional stability frequency (fk), and maximum oscillation frequency (fmax) have been discussed comprehensively. Hence, the optimal layout geometry is addressed by the Figure of Merit (FoM). Results of this thesis provide valuable information to design 90 nm RF MOS transistor.
其他識別: U0005-2107200917405300
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