Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8614
標題: 90奈米雙閘極疊接電晶體之射頻特性分析與其應用
Application and characterization on Dual-Gate transistor in 90-nm RF CMOS technology
作者: 楊智文
Yang, Chih-Wen
關鍵字: Dual-Gate transistor;雙閘極電晶體;Mixer;混波器
出版社: 電機工程學系所
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摘要: 
本論文分為兩部份,第一部份研究在疊接架構電路中,雙閘極電晶體與傳統單閘極電晶體之差異,並另外提出一種佈局模式可以降低元件消耗功率。首先從DC量測結果,探討Dual Gate電晶體四種操作區域特性,並且尋找一組最佳偏壓點,因此在這組偏壓下量測高頻截止頻率、最大的振盪頻率與穩定度。雙閘極電晶體等效寄生電容(閘極端到汲極端和閘極端到源極端之寄生電容總和)比單閘極電晶體減少13.28%,此外基底阻值增加7.7%,因此截止頻率與最大震盪頻率提升9%、14.5%,面積縮小3%。
第二部分研究射頻電路中;使用TSMC CMOS 0.18μm製程,設計5.2GHz高線性度雙平衡式混波器,傳統採用電阻負載的Gilbert Cell架構常受限於低電壓操作,必須再增益、線性度及最大輸出功率作取捨,若改採用電流鏡負載與源極退化電阻方法,則以改善增益同時,線性度仍可維持一定的值,並可將雙端訊號轉由單端輸出以利於量測。最後量測結果,轉換增益為3.19dB、P1dB增益壓縮點為-4dBm、IIP3三階截斷點為8dBm,隔離度RF-to-IF、LO-to-IF、LO-to-RF分別為-35dBm、-27dBm、-33dBm,電路消耗功率為6.59mW。

This thesis includes two parts. The first part demonstrates that the cacode configuration of Dual Gate MOS transistor and compares the difference between conventional single gate MOS transistor. The proposed layout could reduce the device power consumption. Based on the DC measurement, we can understand the four characteristics of the dual gate transistors at the operational region and achieve an optimal bias condition. Therefore, using these bias voltages, we compare the cut-off frequency, the maximum oscillation frequency and the stability. The parasitic capacitance of Dual Gate MOS transistor is 13.28% smaller than the conventional single gate MOS transistor. Moreover, the substrate impedance is 7.7% lager than conventional type. Therefore, the cut-off frequency and the maximum oscillation frequency have been increased by 9% and 14.5%.
In RF circuit, both 5.2GHz high-linearity mixer and a Gilbert Cell were implemented by TSMC CMOS 0.18μm process.The Gilbert Cell mixer of resistive loading is restricted by supply voltage, thus, this architecture has to trade off between conversion gain and linearity. In this literature, the methods of alternatively active loading and source degeneration were developed for improving conversion gain and linearity simultaneously. In addition, the topology of active loading also could replace different output with single-ended output and make measure easily. This design performed 3.19dB conversion gain with 6.59mW power consumption. The linearity results were -4dBm P1dB and IIP3 of 8dBm.
URI: http://hdl.handle.net/11455/8614
其他識別: U0005-2207200916193000
Appears in Collections:電機工程學系所

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