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|標題:||IEEE 802.11n 多碼率低密度同位元查核碼解碼器之設計
Design of IEEE 802.11n Multi-Rate LDPC Code Decoder
|關鍵字:||LDPC;多碼率;IEEE 802.11n;Multi-Rate;decoder;低密度同位元查核碼;解碼器||出版社:||電機工程學系所||引用:|| A.J. Blanksby, C.J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 404-412, March 2002.  T. Brack, F. Kienle, N. Wehn, “Disclosing the LDPC code decoder design space,” in Proc. Design, Automation and Test in Europe, March 2006, vol. 1, pp. 6.  M.M. Mansour, N.R. Shanbhag, “High-throughput LDPC decoders,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 976-996, Dec. 2003.  IEEE Std 802.16e™-2005. “IEEE Standard for Local and metropolitan area networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands and Corrigendum 1” IEEE Std 802.16e-2005—Approved 7 December 2005; ieeexplore.ieee.org.  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Yohena, H. Shimajiri, T. Yoshida, M. Kurosaki, B. Sai, H. Ochi, “Performance Evaluation of Low Density Parity Check Codes for IEEE 802.11n and Its ASIC Design,” in Proc. International Symposium on Communications and Information Technologies, pp. 609-614, Oct. 2008.  M. Rovini, G. Gentile, F. Rossi, L. Fanucci, “A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes,” in Proc. IEEE Global Telecommunications Conference, pp. 3270-3274, Nov. 2007.||摘要:||
低密度同位元查核碼（LDPC Codes）的錯誤更正效能非常好，使得未來幾代的無線通訊系統得以實現更高的速率。本論文提出了一個高產出量、高平行度、高彈性和高擴展性的非規則低密度同位元查核碼解碼系統的硬體電路，此電路完全符合IEEE 802.11n所規範的標準：三種編碼長度648、1296和1944位元以及四種編碼速率1/2、2/3、3/4和5/6。
此多碼率低密度同位元查核碼解碼器矽智產元件實現在幾個超大型積體電路技術，包括：台積電的0.18微米和聯華電子90奈米製程，另外此架構也被實現在元件可程式化邏輯閘陣列中（XC5VLX330）。我們提出來的多碼率低密度同位元查核碼解碼器與最新的研究相比有下列的優點：（1）完全符合IEEE 802.11n的規範（20/40 MHz）；（2）大約只需要66%的面積；（3）減少22％的編碼能量消耗。
Low-Density Parity-Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This thesis presents a high throughput, parallel, scalable and irregular LDPC decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296 and 1944 bits and coding rate 1/2, 2/3, 3/4 and 5/6 based on IEEE 802.11n standard.
Our proposed LDPC decoder is a parameterize IP core running the well-known TDMP and SMSA decoding algorithm. The decoder works in pipeline, very effective technique to rearrange the sequence of its elaborations is proposed in order to minimize the iteration latency, and our proposed reducing switch activity algorithm reduces active node switching activities to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. Moreover, we further improved the design with pipeline structure, parallel computation and no memory unit. Therefore, we can decode six different codewords at same time and only use one routing network to route data.
The prototype architecture is being implemented on several VLSI technologies (TSMC 0.18 um and UMC 90 nm) and tested on the Xilinx Virtex-5 (XC5VLX330) FPGA. The proposed multi-rate LDPC decoder has the following advantages when compared to recent state-of-the-art architectures: (1) fully support IEEE 802.11n specification (20/40 MHz); (2) smaller normalized area about 66% in average; (3) reduced about 26% normalized energy.
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