Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8655
標題: 應用於低電壓之多級電荷幫浦電路的設計與分析
Design and Analysis of Multi-Stage Charge Pumps for Low-Voltage Applications
作者: 許建斌
Hsu, Chien-Pin
關鍵字: charge pump;電荷幫浦
出版社: 電機工程學系所
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摘要: 
電荷幫浦電路廣泛應用於快閃記憶體、電子抹除式記憶體、液晶螢幕顯示器的驅動電路和三維立體超大型積體電路上。近年來很多電荷幫浦電路相繼提出,這些電路都是針對臨界電壓和本體效應對Dickson 電荷幫浦造成的效能減低的改良。然而,若只使用PMOS電晶體來設計正電壓幫浦電路,則使用N-well CMOS製程便可將臨界電壓和本體效應降到最低,並且可以減少晶片面積。本論文提出一個二相位正電壓PMOS電荷幫浦電路,這個電荷幫浦使用了兩個輔助時脈來提高電晶體的閘極電壓,進而提升幫浦電路的推動能力。 在0.18 μm CMOS 製程下,四級的電荷幫浦電路工作在1伏特時,輸出的電壓增益可達到90%以上。
此外,我們使用了前面所提出的輔助時脈電路來改良Racape 和 Daga 電荷幫浦電路推動能力不足和電源電壓過高的缺點。此改良式的電荷幫浦電路在0.35 和0.18 μm CMOS 製程下,電壓增益和效率最高分別提升了30% 和20%。
當電源電壓逐漸下降,電晶體的導通電阻將會非線性的增加,而且不同的電荷幫浦電路的開關電晶體的閘極電壓亦不盡相同。所以傳統的兩種電荷幫浦輸出電壓公式,無法正確估算工作於低電壓時的幫浦輸出電壓值。於是我們針對我們所提出的PMOS幫浦電路和倍壓電路(voltage doubler)中每一級的電荷傳遞波形加以分析,分別推導出兩個較精確的輸出電壓公式。 同時,我們也更詳盡的探討雜散電容對幫浦電路效率的影響進而推導出兩個效率公式。在0.18 μm CMOS 製程下,輸出電壓和效率兩種公式的預測值接近模擬和量測的結果。最後,依據所提出的電壓和效率公式,我們提出一種最佳化的電荷幫浦設計方法,只要適當的選取電晶體的長寬比、電容大小、操作頻率及幫浦級數等參數,即可以設計出最高效率的電荷幫浦。

Charge pump circuits are widely applied to flash memories, EEPROM, LCD, and 3D VLSI, and so on. In recent years, many charge pumps have been proposed to reduce the effects of the body effect and threshold voltage of the Dickson charge pump as the number of sages is increased. However, if only PMOS is used in positive charge pumps, N-wells are easy to implement and the threshold voltages and body effects can be reduced. In this dissertation, we propose a positive two-phase PMOS charge pump with two auxiliary clocks to boost the gate biases of the switching transistors. The proposed four-stage PMOS charge pump has high driving capability and achieves a voltage gain of more than 90% with no load at a supply voltage of 1 V using 0.18 μm CMOS technology.
Another modified Racape and Daga''s PMOS charge pump is also proposed to increase overdrive voltages of the switching transistors and to reduce supply voltage. Simulation results show that the proposed two-stage modified Racape and Daga's PMOS charge pump improves the voltage gain by more than 30% for 0.35 μm CMOS technology and improves the maximum power efficiency by 20% for 0.18 μm CMOS technology in comparison with Racape and Daga''s charge pump.
As supply voltage trends lower, the conventional output voltage models cannot accurately estimate the output voltage of charge pumps due to the increasing on-resistance of switching transistors. Moreover, the charge transfer voltage waveforms of various charge pumps are different because of the various gate bias conditions. In this dissertation, accurate analytical models of the output voltage for voltage doubler and proposed PMOS charge pumps are derived based on the voltage waveforms of each pumping stage. Compact power efficiency models for voltage doublers and proposed PMOS charge pumps are also proposed. The proposed output voltage and power efficiency models agree well with simulation and measurement results for these two charge pumps using 0.18 μm CMOS technology. Finally, a design methodology that is based on these models is developed to determine the transistor sizes, the pumping capacitance, the frequency, and the number of stages that maximize power efficiency.
URI: http://hdl.handle.net/11455/8655
其他識別: U0005-2701201004405700
Appears in Collections:電機工程學系所

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