Please use this identifier to cite or link to this item:
標題: 應用類比電路之晶片內建終端控制器
On-die-termination control using analog circuits
作者: 廖培享
Liao, Pei Hsiang
關鍵字: 晶片內建終端控制器;ODT
出版社: 電機工程學系所
引用: [1] [2]. “DDR SDRAM Technical Note” . in Micro Electronics,Sep. 2001 [3]. “DDR2 SDRAM Technical Note”. in ELPIDA Electronics,April. 2007. [4] H. Conrad,“2.4 Gbits/s CML I/Os with integrated line termination resistors realized in 0.5-_m BICMOS technology,” in Proc.Bipolar/BiCMOS Circuits and Technology Meeting,Sept. 1997, pp.120–122. [5]. Kyoung-Hoi Koo, Soo-Kyung Lee, Jin-Ho Seo, Myeong-Lyong Ko and Jae-Whui Kim ,”A Versatile I/O with Robust Impedance Calibration for Various Memory Interfaces”Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium , Sep. 2006 [6] J. Griffin and D. Johnson,“Large-signal active resistor output driver,” in Proc. 42nd Midwest Symp. Circuits and Systems,vol. 2,1999,pp.706–709. [7]. Yongping Fan and Jeffrey E. Smith,” On-Die Termination Resistors With Analog Impedance Control for Standard CMOS Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS,vol. 38,NO. 2,FEBRUARY 2003. [8]. “DDR Data sheet” in Micro Electronics. [9]. “DDR2 Data sheet” in Micro Electronics. [10] B. Razavi,“ Design of Analog CMOS Integrate Circuit “,New York,NY: McGRAW-Hill,2001. [11] M. Aoki, J. Etoh, M. Horiguchi, S. Ikenaga, K. Itoh, K. Kajigaya,H. Kotani, T. Matsumoto, K. Ohshima, and H. Tanaka, “A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier,”IEEE J. Solid-State Circuits, vol. 25, pp. 1129–1135, Oct. 1990. [12] P. R. Gray et al., “Analysis and Design of Analog Integrated Circuits, 3rd ed. New York: Wiley, 1993.Authorized licensed [13] 廖春成,” Circuit design of step-down voltage regulators for Embedded EEPROM”,NCHU, June 2007 [14] Lee Sung-Dae,Lee Won-Hyo and Chung Kang-Min,” A Highly Linear Voltage Controlled Resistor For Neural Chip”,IEEE,January,1998 [15] “Hspice manual” [16]
為了提升訊號品質,達到降低晶片間經由資料匯流排的反射訊號,使用termination已經是目前主機板設計中,不可或缺的技術。傳統上,termination以電阻製作,不但佔用主機板面積,而且溫度變化以及製程漂移造成電阻值變動,降低termination的效果。ODT (On-die Termination)是目前最常見的方式,除了節省主機板空間外,對於溫度變化以及製程漂移造成電阻值變動,仍無法避免。
針對溫度變化以及製程漂移造成電阻值變動,本篇論文將提出NMOS ODT電路加入運算放大器(OP)補償電路的方式,以增加電阻值的線性度,減小阻值的變動,同時提出設計此ODT中電晶體大小的原理。結合NMOS 和PMOS ODT電路加入OP補償電路的方式,可以更完整的降低資料匯流排上pull-up、pull-down訊號和晶片之間的反射訊號,提升訊號品質。

In order to enhance signal quality, to reduce the chip via the data bus between the reflection signal, the use of termination is already the existing motherboard design, an indispensable technology. Traditionally, termination in order to create resistance, not only occupied the motherboard area, but also changes in temperature and process shift caused by changes in resistance value to reduce the effect of termination. ODT (On-die Termination) is the most common way, in addition to saving board space, as well as the manufacturing process for the temperature shift caused by changes in resistance value is still unavoidable.
For temperature changes and process changes in resistance value caused by shift, this paper will propose adding NMOS ODT circuit operational amplifiers (OP) compensation circuit means to increase the resistance value of linearity, reduced resistance to change, and propose ODT's MOS size of design priciple. Combination of NMOS and PMOS ODT circuit by adding OP compensation circuit, it can be more complete reduction of the data bus pull-up, pull-down signal and the reflected signals between the chips to improve signal quality.
In addition, through replication ODT gate potential way to compensate for only one group OP reference circuit and an external resistor, which can provide multiple signals need to termination of the client to use, to save space and cost requirements.
其他識別: U0005-2801201016571900
Appears in Collections:電機工程學系所

Show full item record
TAIR Related Article

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.