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標題: 基於四分之一壓縮技術之低複雜度直接數位頻率合成器架構設計與性能分析
Architecture design and performance analysis of a low complexity direct digital frequency synthesizer based on quadrant compression technique
作者: 張元庭
Chang, Yuan-Ting
關鍵字: 直接數位頻率合成器;DDFS;鎖相迴路;PLL
出版社: 電機工程學系所
引用: [1] Roland E.Best,”Phase-Locked Loop:Design,Simulation & Applications,”Third Edition,McGraw-Hall Inc.,1993. [2]陳光原,”The Design and Implementation of a 3.3v 400MHz All Digital Phase - Locked Loop,”Master Thesis,Tamkung University,1997. [3] J.Vankka,”Methods of mapping from phase to sine amplitude in direct digital sy- nthesis,” IEEE Int.Frequency Control Symp.,pp.942-950,Jun2 1996. [4] E.De Caro,E.Napoli,and Strollo A.M.G.,”ROM-less direct digital frequency syn- thesizes exploiting polynomial approximation,” 9th International Conference on Electronics,Circuits and System,vol.2,pp.481-484,Sept.2002. [5] A. M. Sodagar,and G.R.Lahihi,”A novel architecture for ROM-less sin-output di- rect digital frequency synthesizers by using the 2nd-order parabolic approximation ,” IEEE/EIA Int.Frequency Control Symp.and Exhibition,pp.284-289,June 2000. [6] Lai Lin-hui,Li Xiao-jin,Lai Zong-sheng,” ALow-Complexity Direct Digital Freq- uency Synthesizer,”in IEEE 2008. [7] C. Meenakam and A. Thanachayanont,” A ROM-Less Direct Digital Frequency Synthesiser Using a Polynomial Approximation,”in IEEE 2003. [8] Bar-Giora Goldberg,”Digital Frequency Synthesis Demystified ,” Chapter7 Look- up Table and Sine ROM Compression. [9] Byung-Do Yang, Ki-Hyuk Sung, Young-Joon Kim, Lee-Sup Kim,Seon-Ho Han, and Hyun-Kyu Yu,”A Direct Digital Frequency Synthesizer Using A New ROM Compression Method,” in IEEE. [10] Fa Foster Dai, Senior Member, IEEE, Weining Ni, Shi Yin, Member, IEEE, and Richard C. Jaeger, Fellow, IEEE,” A Direct Digital Frequency Synthesizer With Fourth-Order Phase Domain _ Noise Shaper and 12-bit Current-Steering DAC,” in IEEE 2006. [11] Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin,”A Low-Power Eff- icient Direct Digital Frequency Synthesizer Based On New Two-Level Lookup Table,” in IEEE 2006. [12] Xiaojin Li, Linhui Lai, Ao. Lei and Zongsheng Lai,”A Memory-Reduced Direct Digital Frequency Synthesizer for OFDM Receiver Systems,” in IEEE Transact- ions on Consumer Electronics, Vol. 54, No. 4, November 2008. [13] Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, and Hyun-Kyu Yu,” An 800-MHz Low-Power Direct Digital Frequency Synthesizer With an On -Chip D/A Converter,” in IEEE Journal Of Solid-State Circuits, VOL. 39, NO. 5, MAY 2004. [14] Jen-Chuan Chih,Jun-Yei Chou, Sau-Gee Chen,” An Efficient Direct Digital Fre- quency Synthesizer Based On Two-Level Table Lookup,” in IEEE International Frequency Control Symposium and PDA Exhibition,in 2001. [15] Ashkan Ashrafi, Reza Adhami, Laurie Joiner, and Parisa Kaveh,” Arbitrary Wa- veform DDFS Utilizing Chebyshev Polynomials Interpolation,”in IEEE Transac- tions On Circuit And Systems -I: Regular Papers, VOL. 51, NO. 8, August 2004. [16] Aqib Perwaiz, Shoab A Khan,“Bit Serial CORDIC DDFS Design For Serial Dig- ital Down Converter,”in Australasian Telecommunication Networks and Applic- ations Conference December 2nd – 5th 2007, in2007. [17] Shiann-Shiun Jeng, Hsing-Chen Lin, and Chen-Yu Wu,”DDFS Design Using the Equi-Section Division Method for SDR Transceiver,”in IEEE 2008. [18] Antonio G.M. Strollo, Ettore Napoli, Davide De Caro,”Direct Digital Frequency Synthesizers using First-Order Polynomial Chebyshev Approximation,” in ESS -CIRC 2002. [19] Muhammad Nadir khan, Muhammad Saad Imran, Muhammad Rehan, Usman Ha -i,”High Speed Direct Digital Frequency Synthesizer(DDFS) Architecture With Reduced ROM Structure,”. [20] H.Jafari, A.Ayatollahi, S.Mirzakuchaki,”A Low Power, High SFDR, ROM-Less Direct Digital Frequency Synthesizer,”in IEEE 2005. [21] Abdellatif Bellaouar, Michael S. O’brecht, Amr M. Fahim, Mohamad I.Elmasry , ”Low-Power Direct Digital Frequency Synthesis for Wireless Communication,” in IEEE Journal Of Solid-State Circuits, VOL. 35, NO. 3, March 2000. [22] Alin Grama, Gabriel Muntean,” Direct Digital Frequency Synthesis implemented On a FPGA Chip,” in IEEE 2006. [23] J. M. Pierre Langlois, and Dhamin Al-Khalili,” Novel Approach to the Design of Direct Digital Frequency Synthesizers Based on Linear Interpolation,” in IEEE Transactions On Circuits And System - II: Analog And Digital Signal Processing , VOL. 50, NO. 9, September 2003.
本篇論文將各種直接數位頻率合成器的架構採用場式可規劃化邏輯閘陣列(FPGA)的硬體實現與分析,且將直接數位頻率合成器的架構分為有唯讀記憶體(ROM)與無唯讀記憶體(ROM_less) 的方式,其中有唯讀記憶體的架構有不採用壓縮技術且查表方式、四分之一壓縮技術且查表技術、八分之一壓縮技術且查表技術;另外無唯讀記憶體的架構為利用多項式方程式(polynomial equation)來實現。綜合以上提出的架構後,本篇依低複雜度硬體的需求設計並修改成四分之一壓縮與積化和差結合架構,與四分之一壓縮與積化和差結合近似法管線化架構。

In this thesis, we aim at the studies of a low complex direct digital frequency synthesizer (DDFS) design and its functional analysis. Direct digital frequency synthesizer is a sine-wave generator with the function of fast fine turning and can generate digital sinusoidal values. Phase-locked loop (PLL) is the main traditional frequency synthesizer and its advantages are the high signal purity and the broad switched bandwidth. However, it can't provide a small frequency and a fast rate at switching. Compare the advantages and disadvantages between both two schemes, we find that the DDFS can overcome the drawbacks of the PLL.
We realize the hardware architectures of various DDFSs and synthesize the designs with a field programmable gate array (FPGA). Besides, the architectures of the DDFS can be divided into two categories, which are the read-only memory (ROM) based and the non read-only memory based (ROM_less) architectures. In the ROM based architecture, three common used schemes are described as follows: the non-compression table method, the quarter compression table method, and the eighth compression table method. In the ROM_less architecture, the polynomial equation based scheme is popularly applied to process the digital sinusoidal values. After the above architectures are studied, we propose two modified schemes which are a combined quarter compression and product-to-sum architecture and a combined quarter compression and product-to-sum architecture with the approximate pipeline.
By comparing the realization results and completely analyzing different architectures, we find that the combined quarter compression and product-to-sum method with the approximate pipeline has better efficiency than the others.
其他識別: U0005-2807200922193300
Appears in Collections:電機工程學系所

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