Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8742
標題: 使用超取樣及具有頻率校正技術之2.5Gb/s時脈資料回復電路
A 2.5Gb/s Clock and Data Recovery Circuit Using Oversampling and Frequency-Calibrated Techniques
作者: 林威碩
Lin, Wei-Shuo
關鍵字: phase-locked loop;鎖相迴路;clock and data recovery;oversampling;frequency-calibrated;delta-sigma modulator(DSM);時脈資料回復電路;超取樣;頻率校正;三角積分調變器
出版社: 電機工程學系所
引用: [1]ITRS, “International Technology Roadmap for Semiconductors 2007 Edition: Assembly and Packaging,” International Technology Roadmap for Semiconductors (ITRS), http://www.itrs.net, 2007. [2]C.-K Yang and M. Horowitz, “A 0.8μm CMOS 2.5 Gbps oversampling receiver and transmitter for serial links,” IEEE Journal of Solid-State Circuits, vol.31, Dec.1996. [3]S.-C. Hwu, “Burst-Mode Clock and Data Recovery Circuit for Passive Optical Networks,” M.S. Thesis National Taiwan University, July 2005. [4]B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003. [5]G. Kramer, G. Pesaventom, Alloptic, Inc., “Ethernet Passive Optical Network(EPON): Building a Next-Generation Optical Access Network,” IEEE Communication Magazine, Topics in LIGHTWAVE, pp. 66-73, Feb. 2002 [6]F. M. Gardner, “Charge-pump phase-lock loop,” IEEE Trans. Comm., vol COM-28, pp. 1849-1858, Nov, 1980. [7]M. V. Paemel, “Analysis of a charge-pump PLL: a new model,” IEEE Trans. Comm., vol, no. 7, pp. 2490-2498, July 1994. [8]J. Yuan and C. Svensson, “Fast CMOS nonbinary divider and counter,” Electronics Letters, pp. 1222-1223, June 1993. [9]J. Yuan and C. Svensson, “High speen CMOS circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989. [10]C. Y. Yang, G. K. Dehng, J. M. Hsu, and S. I. Liu, “New dynamicflip-flops for high-speed dual-modulus prescaler,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1568-1571, Oct. 1998. [11]C. Y. Yang, J. W. Chen, Meng-Ting Tsai, “A High-Frequency Phase-Compensation Fraction-N Frequency Synthesizer,” IEEE International Symposium on Circuits and Systems, May. 2005. [12]S.E. Meninger, M.H. Perrott, “A fraction-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization- induced phase noise,” IEEE Transaction on Circuits and System-II: Analog and Digital Signal Processing, Vol.50, no. 11, Nov. 2003. [13]B. Miller and R. J. Conley, “A Multiple Modulator Fractional Divider,” IEEE Transactions on Instrumentation and Measurement, Vol. 40, no. 3, June 1991. [14]B. Bornoosh, A. Afali-Kusha, R. Dehghani, N. Mehrara, S.M. Atarodi and M. Nourani, “Reduced complexity 1-bit higher-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesizer application,” IEEE Proc. Circuits Devices System, vol. 152, no. 5, October 2005. [15]C. R. Hogge, “A self correcting clock recovery circuit,” IEEE J. Lightwave Technology, vol.3, pp. 1312-1314, Dec. 1985. [16]B. Stilling, “Bit rate and protocol independent clock and data recovery,” Electronics Letters, vol.36, pp. 824-825, Apr. 2000. [17]T. M. Lee, et al., “A 155MHz clock recovery delay and phase locked loop,” IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1736-1746, Dec. 1992. [18http://www.altera.com/support/devices/pll_clock/jitter/pll-jitter.html [19]http://www.maxim-ic.com/appnotes.cfm/appnote_number/377 [20]A. Pottbäcker, U. Langmann, and H.-U. Schreiber, “A Si Bipolar Phaseand Frequency Detector IC for Clock Extraction Up to 8 Gb/s,” IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992. [21]J. C. Scheytt, G. Hanke, and U. Langmann, “A 0.155-, 0.622, and 2.488-Gb/s Automatic Bit-Rate Selecting Clock and Data Recovery IC for Bit-Rate Transparent SDH Systems,” IEEE Journal of Solid-State Circuits, vol.34, no. 12, pp. 1935-1943, Dec. 2003. [22]L. Henrickson, D. Shen, U. Nellore, A. Ellis, J. Oh, H. Wang, G. Cpriglione, A. Atesoglu, A. Yang, P. Wu, S. Quadri, and D. Crosbie, “Low PowerFully Integrated 10-Gb/s SONET/SDH Transceiver in 0.13-mm CMOS,” IEEE Journal of Solid State Circuits, vol. 38, no. 10, pp. 1595-1601, Oct.2003.- [23]H. S. Muthali, T.P. Thomas, and I.A. Young, “A CMOS 10-Gb/s SONET Transceiver, “ IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1026-1033, Jul. 2004. [24]B. Razavi, “Challenges in the Design of High-Speed Clock Data Recovery Circuit,” IEEE Communication Magazine, pp. 94-101, Aug. 2002. [25]R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery inSerial Data Transmission Systems (Book style with paper title and editor),” Phase-Locking in High-Performance Systems from Devices to Architectures, B. Razavi, Ed. New Jersey: John Wiley & Sons, Inc., 2003, pp.34-45, 2003. [26]A. Pottbäcker, U. Langmann, and H.-U. Schreiber, “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction Up to 8 Gb/s,” IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992. [27]X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS Data Recovery DLL Using Half-Frequency Clock,” IEEE Journal of Solid-State Circuits, vol. 37, no. 6, pp. 711-715, Dec. 2002. [28]H.-H. Chang, R.-J. Yang, and S.-I. Liu, “Low Jitter and Multirate Clock and Data Recovery Circuit Using a MSADLL for Chip-to-Chip Interconnection,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 12, pp. 2356-2364, Dec. 2004. [29]J. L. Sonntag and J. Stonick, “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links,” IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1867-1875, Aug. 2006. [30]M. H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, and B. Del Signore, “A 2.5-Gb/s Multi-Rate 0.25-mm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2930-2944, Dec. 2006. [31]R. Kreienkamp, U. Langmann, C. Zimmermann, T. Aoyama, and H. Siedhoff, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with an Analog Phase Interpolator,” IEEE Journal of Solid-State Circuits, vol. 40,no. 3, pp. 736-743, Mar. 2005. [32]M.Y. He and J. Poulton, “A CMOS Mixed-Signal Clock and Data Recovery Circuit for OIF CEI-6G 1 Backplane Transceiver,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 597-606, Mar. 2006. [33]M. Hsieh and G.E. Sobelman, “Clock and Data Recovery with Adaptive Loop Gain for Spread Spectrum SerDes Applications,” IEEE International Symposium on Circuits and Systems, pp. 4883-4886, May 2005. [34]H.-T. Ng, R. Farjad-Rad, M.-J. E. Lee, Member, W.J. Dally, T. Greer, J. Poulton, J.H. Edmondson, R. Rathi, and R. Senthinathan, “A Second-Order Semidigital Clock Recovery Circuit Based on Injection Locking,” IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2101-2110, Dec. 2003. [35]R. Farjad-Rad, A. Nguyen, J. M. Tran, T. Greer, J. Poulton, W. J. Dally, J.H. Edmondson, R. Senthinathan, R. Rathi, M.-J.E. Lee, and H.-T. Ng,“A 33-mW 8-Gb/s CMOS Clock Multiplier and CDR for Highly Integrated I/Os,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1553-1561, Sept. 2004. [36]M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, “A 10 Gb/s burst-mode CDR IC in 0.13 mm CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2005. [37]A. Tajalli, P. Muller, M. Atarodi, and Y Leblebici, “A Multichannel 3.5mW/Gbps/Channel Gated Oscillator Based CDR in 0.18 mm Digital CMOS Technology,” Proceedings of the 31st European Solid-State Circuits Conference, Sept. 2005. pp. 193-196. [38]A. Tajalli, P. Muller, and Y. Leblebici, “A Power-Efficient Clock and Data Recovery Circuit in 0.18um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2235-2244, Oct. 2007. [39]J. Kim and D.-K. Jeong, “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling,” IEEE Communication Magazine, pp. 68-74, Dec. 2003. [40]S.I. Ahmed and T.A. Kwasniewski, “Overview Of Oversampling Clock and Data Recovery Circuits” Canadian Conference on Electrical and Computer Engineering, pp. 1876-1881, May 1-4, 2005. [41]M. Ierssel, A. Sheikholeslami, H. Tamura, and W.W. Walker, “A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2224-2234, Oct. 2007. [42]S.-H. Lee, M.-S. Hwang, Y. Choi, S. Kim, Y. Moon, B.-J. Lee, D.-K. Jeong, W. Kim, Y.-J. Park, and G. Ahn, “A 5-Gb/s 0.25- m CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1822-1830, Dec. 2002. [43]P. K. Hanumolu, M.G. Kim, G.-Y. Wei, and U.-K. Moon, “A 1.6 Gbps Digital Clock and Data Recovery Circuit,” IEEE Custom Integrated Circuits Conference, pp. 603-606, Sept. 2006. [44]D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L, DeVito, “12.5-Mb/s to 2.7-Gb/s Continuous-Rate CDR with Automatic Frequency Acquisition and Data-Rate Readback,” IEEE Journal of Solid-State Circuits, vol. 40, no.12, pp. 2713-2725, Dec. 2005. [45]W. Rhee, H. Ainspan, S. Rylov, A. Rylyakov, M. Beakes, D. Friedman, S. Gowda, M. Soyuer, “A 10-Gb/s CMOS Clock and Data Recovery Circuit Using a Secondary Delay-Locked Loop,” Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, pp. 81-84. Sept. 2003. [46]P. Larsson, “A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability,” IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1951-1999, Dec. 1999. [47]J. Lee and M. Liu, “A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique,” IEEE International Solid-State Circuits Conference,Feb. 2007. [48]K. Schneider and H. Zimmermann, “Highly Sensitive Optical Receivers,” Springer Berlin Heidelberg, New York, 2006. [49]B. Analui, and A. Hajimiri, “Instantaneous Clockless Data Recovery and Demultiplexing,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 8, pp. 437-441, Aug. 2005. [50]J. Kenney, D. Dalton, M. Eskiyerli, E. Evans, B. Hilton, D. Hitchcox, T. Kwok, D. Mulcahy, C. McQuilkin, V. Reddy, S. Selvanayagam, P. Shepherd, W. Titus, and L. DeVito, “A 9.95 to 11.1Gb/s XFP Transceiver in 0.13 mm CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2006. [51]C.-H. Liang, S.-C. Hwu, and S.-I. Liu, “A 2.5 Gbps Burst-Mode Clock and Data Recovery Circuit,” IEEE Asian Solid-State Circuits Conference, Nov. 2005. pp. 457-460. [52]C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, Z. Wamg, “A family of low-power truly modular programmable dividers in standard 0.35-um CMOS technology,” IEEE J. of Solid-State Circuits, Vol.35, pp.1039-1045, July 2000.
摘要: 
近年來,光纖通訊系統被應用在各種傳輸介面當中,例如來源同步時序介面(Source Synchronous Timing)和來源非同步時序介面(Source Asynchronous Timing)。在來源非同步時序介面當中,由於傳送端和接收端之間容易有頻率上的誤差,這些誤差會累積成輸出的抖動,造成輸出抖動變大,本論文中將討論具有頻率校正技術的時脈資料回復電路,文章主要分成四大部分。
首先,第一部份將會介紹基本的光纖通訊架構和其研究背景。
第二部份,我們會分別介紹整數-N鎖相迴路和非整數-N鎖相迴路,然後再引進時脈資料回復電路,將近年來時脈資料回復電路的架構一一做介紹以及比較它們的優缺點。
第三部份我們將實作一個使用三階三角積分調變技術的4GHz非整數型鎖相迴路,其製程是使用台積電0.18微米互補式金氧半導體,晶片面積為1.4mm 1.4mm。外部參考頻率為77MHz,中心頻率鎖定在3.927GHz,鎖相迴路其相位雜訊在1MHz的偏差下為-94.2dBc/Hz,鎖定時間為11μs,消耗功率在操作電壓為1.8V時為28mW。
第三部份我們將藉由上一顆晶片的成果,提出一個使用超取樣及具有頻率校正技術之2.5Gb/s時脈資料回復電路,此電路相較於傳統的超取樣時脈資料回復電路,它可以藉由內部的三角積分調變鎖相迴路去追隨輸入資料的速率,藉此達到頻率校正的目的。其製程是使用台積電0.18微米互補式金氧半導體,晶片面積為1.33mm 1.38mm。外部參考頻率為96MHz,中心頻率為2.4GHz,可校正的頻率範圍為 MHz,而壓控震盪器在無外部控制下其相位雜訊在1MHz的偏差下為-121.54dB/c,鎖定後其相位雜訊在1MHz的偏差下為-123.74dB/c,鎖定時間為20μs,消耗功率在操作電壓為1.8V時為152mW。

Optical communication systems have been applied in many transmission interface recently, such as source synchronous timing and source asynchronous timing. Jitter will be accumulated for source asynchronous timing, because the frequency offset exists between transmitter and receiver. This thesis describes a clock and data recovery circuit with a frequency calibration technique. It is divided into four parts.
At first, the thesis introduces Optical Network and the research background. The second part describes the integer-N phase-locked loop (PLL) and fraction-N phase-locked loop, and then we introduce clock and data recovery (CDR) circuits and compare different circuit architectures.
In the third part, a 4GHz fraction-N PLL is been realized using 3rd-delta-sigma modulator. This chip is fabricated in tsmc 0.18μm CMOS process, and total area is 1.4mm 1.4mm. The reference signal clock is 77MHz, and the center frequency is 3.927GHz. The phase noise with 1MHz offset measured in voltage-controlled oscillator (VCO) and phase-locked loop is -112dBc/Hz and -94dBc/Hz, respectively. The locking time is 11μs, and the power consumption is 28mW with 1.8V.
In the last part, a 2.5Gb/s clock and data recovery using oversampling and frequency-calibrated is proposed. The offset-frequency calibrated technique is based on the delta-sigma modulated phase-locked loop topology that can tracking data rate. This chip is fabricated in tsmc 0.18m CMOS process, and total area is 1.33mm 1.38mm. The reference signal clock is 96MHz, and the center frequency is 2.4GHz. The phase noise with 1MHz offset measured in VCO and PLL is -121.54dBc/Hz and -123.79dBc/Hz, respectively. CDR calibration range is MHz and the locking time is 20μs. The power consumption is 152mW with 1.8V.
URI: http://hdl.handle.net/11455/8742
其他識別: U0005-3101201020043700
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.