Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8742
DC FieldValueLanguage
dc.contributor劉堂傑zh_TW
dc.contributor黃崇禧zh_TW
dc.contributor.advisor楊清淵zh_TW
dc.contributor.advisorChing-Yuan Yangen_US
dc.contributor.author林威碩zh_TW
dc.contributor.authorLin, Wei-Shuoen_US
dc.contributor.other中興大學zh_TW
dc.date2011zh_TW
dc.date.accessioned2014-06-06T06:42:04Z-
dc.date.available2014-06-06T06:42:04Z-
dc.identifierU0005-3101201020043700zh_TW
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dc.identifier.urihttp://hdl.handle.net/11455/8742-
dc.description.abstract近年來,光纖通訊系統被應用在各種傳輸介面當中,例如來源同步時序介面(Source Synchronous Timing)和來源非同步時序介面(Source Asynchronous Timing)。在來源非同步時序介面當中,由於傳送端和接收端之間容易有頻率上的誤差,這些誤差會累積成輸出的抖動,造成輸出抖動變大,本論文中將討論具有頻率校正技術的時脈資料回復電路,文章主要分成四大部分。 首先,第一部份將會介紹基本的光纖通訊架構和其研究背景。 第二部份,我們會分別介紹整數-N鎖相迴路和非整數-N鎖相迴路,然後再引進時脈資料回復電路,將近年來時脈資料回復電路的架構一一做介紹以及比較它們的優缺點。 第三部份我們將實作一個使用三階三角積分調變技術的4GHz非整數型鎖相迴路,其製程是使用台積電0.18微米互補式金氧半導體,晶片面積為1.4mm 1.4mm。外部參考頻率為77MHz,中心頻率鎖定在3.927GHz,鎖相迴路其相位雜訊在1MHz的偏差下為-94.2dBc/Hz,鎖定時間為11μs,消耗功率在操作電壓為1.8V時為28mW。 第三部份我們將藉由上一顆晶片的成果,提出一個使用超取樣及具有頻率校正技術之2.5Gb/s時脈資料回復電路,此電路相較於傳統的超取樣時脈資料回復電路,它可以藉由內部的三角積分調變鎖相迴路去追隨輸入資料的速率,藉此達到頻率校正的目的。其製程是使用台積電0.18微米互補式金氧半導體,晶片面積為1.33mm 1.38mm。外部參考頻率為96MHz,中心頻率為2.4GHz,可校正的頻率範圍為 MHz,而壓控震盪器在無外部控制下其相位雜訊在1MHz的偏差下為-121.54dB/c,鎖定後其相位雜訊在1MHz的偏差下為-123.74dB/c,鎖定時間為20μs,消耗功率在操作電壓為1.8V時為152mW。zh_TW
dc.description.abstractOptical communication systems have been applied in many transmission interface recently, such as source synchronous timing and source asynchronous timing. Jitter will be accumulated for source asynchronous timing, because the frequency offset exists between transmitter and receiver. This thesis describes a clock and data recovery circuit with a frequency calibration technique. It is divided into four parts. At first, the thesis introduces Optical Network and the research background. The second part describes the integer-N phase-locked loop (PLL) and fraction-N phase-locked loop, and then we introduce clock and data recovery (CDR) circuits and compare different circuit architectures. In the third part, a 4GHz fraction-N PLL is been realized using 3rd-delta-sigma modulator. This chip is fabricated in tsmc 0.18μm CMOS process, and total area is 1.4mm 1.4mm. The reference signal clock is 77MHz, and the center frequency is 3.927GHz. The phase noise with 1MHz offset measured in voltage-controlled oscillator (VCO) and phase-locked loop is -112dBc/Hz and -94dBc/Hz, respectively. The locking time is 11μs, and the power consumption is 28mW with 1.8V. In the last part, a 2.5Gb/s clock and data recovery using oversampling and frequency-calibrated is proposed. The offset-frequency calibrated technique is based on the delta-sigma modulated phase-locked loop topology that can tracking data rate. This chip is fabricated in tsmc 0.18m CMOS process, and total area is 1.33mm 1.38mm. The reference signal clock is 96MHz, and the center frequency is 2.4GHz. The phase noise with 1MHz offset measured in VCO and PLL is -121.54dBc/Hz and -123.79dBc/Hz, respectively. CDR calibration range is MHz and the locking time is 20μs. The power consumption is 152mW with 1.8V.en_US
dc.description.tableofcontents摘 要 I Abstract III 誌 謝 V 目 錄 VII 圖 目 錄 XIII 表 目 錄 XXI 第一章 序論 1.1研究動機 - 1 - 1.2研究背景及趨勢 - 2 - 1.3論文章節安排 - 6 - 第二章 頻率合成器 2.1簡介 - 7 - 2.2鎖相迴路 - 8 - 2.3整數-N頻率合成器 - 9 - 2.3.1相位頻率偵測器 - 10 - 2.3.2充電泵和迴路濾波器 - 12 - 2.3.3電壓控制震盪器 - 14 - 2.3.4除頻器 - 17 - 2.3.5鎖相迴路的迴路分析 - 18 - 2.4非整數-N頻率合成器 - 21 - 2.5三角積分調變技術 - 25 - 2.6結論 - 30 - 第三章 時脈資料回復電路 3.1簡介 - 31 - 3.2時脈資料回復電路之基礎介紹 - 32 - 3.2.1相位偵測器 - 34 - 3.2.2頻率偵測器 - 35 - 3.3時脈資料回復電路設計考量 - 37 - 3.3.1不歸零資料 - 37 - 3.3.2抖動 - 38 - 3.3.3眼圖 - 39 - 3.3.4位元錯誤率 - 40 - 3.4時脈資料回復電路之架構 - 41 - 3.4.1以鎖相迴路為基底之時脈資料回復電路 - 42 - 3.4.2以延遲鎖定迴路為基底之時脈資料回復電路 - 49 - 3.4.3結合鎖相迴路與延遲鎖定迴路之時脈資料回復電路 - 50 - 3.4.4以相位內插為基底之時脈資料回復電路 - 52 - 3.4.5以注入鎖定為基底之時脈資料回復電路 - 56 - 3.4.6以閘控式震盪器為基底之時脈資料回復電路 - 57 - 3.4.6以超取樣為基底之時脈資料回復電路 - 59 - 3.5結論 - 63 - 第四章 4GHz十六位元三階三角積分調變頻率合成器 4.1簡介 - 65 - 4.2電路架構與考量 - 66 - 4.3內部電路詳述 - 67 - 4.3.1壓控震盪器 - 67 - 4.3.2多模除頻器 - 68 - 4.3.3相頻偵測器 - 69 - 4.3.4充電泵 - 70 - 4.3.5迴路濾波器 - 71 - 4.3.6三角積分調變器 - 72 - 4.4電路模擬 - 77 - 4.4.1 Matlab系統模擬 - 77 - 4.4.2 Hspice電路模擬 - 79 - 4.5規格 - 89 - 4.6量測考量與結果 - 90 - 4.6.1量測考量 - 90 - 4.6.2量測結果 - 91 - 4.7結論 - 95 - 第五章 使用超取樣及具有頻率校正技術之2.5Gb/s時脈資料回復電路 5.1簡介 - 97 - 5.2電路架構的改善與考量 - 99 - 5.2.1 電路架構 - 99 - 5.2.2內部電路與說明 - 100 - 5.3子電路詳述 - 103 - 5.3.1四相位壓控震盪器 - 103 - 5.3.2相位內插電路 - 104 - 5.3.3除頻器 - 104 - 5.3.4正邊緣偵測器 - 105 - 5.3.5相位頻率轉態偵測器 - 105 - 5.3.6計數器 - 108 - 5.3.7決策電路&多工器 - 109 - 5.4電路模擬 - 110 - 5.4.1 Matlab系統模擬 - 110 - 5.4.2 Hspice電路模擬 - 112 - 5.5 規格 - 119 - 5.6 量測考量與結果 - 120 - 5.6.1 量測考量 - 120 - 5.6.2 量測結果 - 122 - 5.7 結論 - 126 - 的六章 結論 6.1 結論 - 127 - 參考文獻 - 129 - 附 錄 - 135 -zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-3101201020043700en_US
dc.subjectphase-locked loopen_US
dc.subject鎖相迴路zh_TW
dc.subjectclock and data recoveryen_US
dc.subjectoversamplingen_US
dc.subjectfrequency-calibrateden_US
dc.subjectdelta-sigma modulator(DSM)en_US
dc.subject時脈資料回復電路zh_TW
dc.subject超取樣zh_TW
dc.subject頻率校正zh_TW
dc.subject三角積分調變器zh_TW
dc.title使用超取樣及具有頻率校正技術之2.5Gb/s時脈資料回復電路zh_TW
dc.titleA 2.5Gb/s Clock and Data Recovery Circuit Using Oversampling and Frequency-Calibrated Techniquesen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
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