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The RF Front-End Design Using Noise Reduction Technique for Dual Band WLAN Applications
|關鍵字:||IEEE802.11a/b/g;IEEE802.11a/b/g;dual band;LNA;Mixer;active balun;noise reduction;雙頻帶;低雜訊放大器;混波器;主動巴倫電路;雜訊抑制||出版社:||電機工程學系所||引用:|| H. Zhang, X. Fan, and E.S. Sinencio, “A Low-Power Linearized Ultra- Wideband LNA Design Technique,” IEEE Journal of Solid-State Circuits, Vol. 44, pp. 320 – 330, February 2009.  S. Joo, T.-Y Choi, and B. Jung, “A 2.4-GHz Resistive Feedback LNA in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits, Vol.44, pp. 3019 – 3029, November 2009.  X. Fan, H. Zhang, and E.S. Sinencio, “A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA,” IEEE Journal of Solid-State Circuits, Vol.43, pp. 588 – 599, March 2008.  M. Ben Amor, A. Fakhfakh, H. Mnif, and M. Loulou, “Dual band CMOS LNA design with current reuse topology,” International Conference on Design and Test of Integrated Systems in Nanoscale Technology 2006 (DTIS 2006), pp. 57 – 61, September 2006.  W.-M. Chang, K.-H. Cheng, and C.F. Jou, “2.45GHz/5.2GHz switched dual-band CMOS LNA with 4 gain control modes,” Asia-Pacific Microwave Conference (APMC2005), Vol.2, pp.4, December 2005.  C.-Y. Kao, Y.-T. Chiang, and J.-R. Yang, “A concurrent multi-band low-noise amplifier for WLAN/WiMAX applications,” IEEE International Conference on Electro/Information Technology (EIT2008), pp. 514 – 517, May 2008.  V. K. Dao, Q. D. Bui, and C.S. Park, “A Multi-band 900MHz/1.8GHz /5.2GHz LNA for Reconfigurable Radio,” RFIC Symposium, pp. 69 – 72, June 2007.  T. K. K. Tsang and M. N. El-Gamal, “Dual-band sub-1 V CMOS LNA for 802.11a/b WLAN applications,” ISCAS Symposium, Vol.1, pp. 217 – 220, May 2003.  L. Belostotski and J.W. Haslett, “Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors,” IEEE Transaction on Circuits and System—I, Regular Papers, Vol.53, pp. 1409 – 1422, July 2006.  T.K. Nguyen, C.H. Kim, G.J. Ihm, M.S. Yang, and S.G. Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Transaction on Microwave Theory and Techniques, Vol.52, pp. 1433 – 1442, May 2004.  D.K. Shaeffer and T.H. Lee, “A 1.5 V, 1.5 GHz CMOS low noise amplifier,” VLSI Circuits Digest of Technical Papers, pp. 32 – 33, June 1996.  Z. Wei, S. Embabi, J.P de Gyvez, and E.S. Sinencio, “Using capacitive cross-coupling technique in RF low noise amplifiers and down-conversion mixer design,” ESSCIRC, pp. 77 – 80, September 2000.  W. Zhuo, X. Li, S. Shekhar, S.H.K. Embabi, J.P. de Gyvez, D.J.Allstot, and E.S. Sinencio, “A capacitor cross-coupled common-gate low-noise amplifier,” TSCII, Vol.52, pp. 875 – 879, December 2005.  X. Li, S. Shekhar, and D.J. Allstot, “Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-μm CMOS,” IEEE Journal of Solid-State Circuits, vol.40, pp. 2609 – 2619, December 2005.  T.K. Nguyen, C.H. Kim, G.J. Ihm, M.S. Yang, and S.G. Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Transaction on Microwave Theory and Techniques, vol.52, pp. 1433 – 1442, May 2004.  H. Samavati, H.R. Rategh, and T.H. Lee, “A 5-GHz CMOS wireless LAN receiver front end,” IEEE Journal of Solid-State Circuits, Vol.35, pp. 765 – 772, May 2000.  V. Aparin, and L.E. Larson, “Modified derivative superposition method for linearizing FET low-noise amplifiers,” IEEE Transaction on Microwave Theory and Techniques, Vol.53, pp. 571 – 581, Feb 2005.  S. Ganesan, E.S. Sinencio, and J.S. Martinez, “A Highly Linear Low- Noise Amplifier,” IEEE Transaction on Microwave Theory and Techniques, Vol.54, pp. 4079 – 4085, December 2006.  A. Mujeeb, S. Yuwono, J.S. Lee, and S.G. Lee, “Highly linear CMOS low noise amplifier with IIP3 boosting technique,” SoC Design Conference ISOCC, Vol.01, pp.414 – 416, November 2008.  L. Jongrit, and N. Won, “Generalized noise analysis of active mixers by simple linear periodic time-varying circuit model,” Custom Integrated Circuits Conference (CICC) , pp. 293 – 296, September 2005.  M.T. Terrovitis, and R.G. Meyer, “Noise in current-commutating CMOS mixers,” IEEE Journal of Solid-State Circuits, Vol.4, pp. 772 – 783, June 1999.  H. Darabi, and J. Chiu, “A noise cancellation technique in active RF-CMOS mixers,” IEEE Journal of Solid-State Circuits, Vol.40, pp. 2628 – 2632, December 2005.  H. Darabi, and A.A. Abidi, “Noise in RF-CMOS mixers: a simple physical model,” IEEE Journal of Solid-State Circuits, Vol.35, pp. 15 – 25, Jan 2000.  C. Yu, and J.S. Yuan, “Linearity and power optimization of a microwave CMOS Gilbert cell mixer,” Electron Devices for Microwave and Optoelectronic Applications (EDMO), pp. 234 – 239, November 2003.  Q. Li, and J.S. Yuan, “Linearity analysis and design optimisation for 0.18 μm CMOS RF mixer,” IEE Proceedings-Devices and Systems, Vol.149, pp. 112 – 118, April 2002.  X. Wang, D. Aykut, and K. Sayfe, “A high IIP3 X-band BiCMOS mixer for radar applications,” ISCAS, Vol.1, pp. 113 – 116, May 2004.  K. Munusamy, and Z. Yusoff, “A Highly Linear CMOS Down Conversion Double Balanced Mixer,” ICSE, pp. 985 – 990, December 2006.  P. Renjing, K.S. Yeo, and Y. Zheng, “A Low-Voltage Low-Power High Linear and Wide-Band Mixer,” ISIC Symposium, pp. 341 – 344, September 2007.  L. Nathawad , M. Zargari, H. Samavati, S. Mehta, A. Kheirkhahi, P. Chen, K. Gong, B. Vakili-Amini, J. Hwang, M. Chen, M. Terrovitis, B. Kaczynski, S. Limotyrakis, M. Mack, H. Gan, M. Lee, S. Abdollahi-Alibeik, B. Baytekin, K. Onodera, S. Mendis, A. Chang, S. Jen, D. Su, and B. Wooley, “A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN,” ISSCC Digest of Technical Papers, pp. 358 – 619, February 2008.  O. Charlon, M. Locher, H.A. Visser, D. Duperray, J. Chen, M. Judson, A.L. Landesman, C. Hritz, U. Kohlschuetter, Yifeng Zhang, C. Ramesh, A. Daanen, Minzhan Gao, S. Haas, V. Maheshwari, A. Bury, G. Nitsche, A. Wrzyszcz, W. Redman-White, H. Bonakdar, Rachid El Waffaoui, and M. Bracey, “A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and bluetooth Co-existence applications,” IEEE Journal of Solid-State Circuits, Vol.41, pp. 1503 – 1512, July 2006.  M. Detratti, E. Lopez, E. Perez, R. Palacio, and M. Lobeira, “Dual-band RF receiver chip-set for Galileo/GPS applications,” IEEE Monterey Symposium, PP. 851 – 859, May 2008.  N. Kim, L.E. Larson, and V. Aparin, “A highly linear SAW-less CMOS receiver using a mixer with embedded Tx filtering for CDMA,” Custom Integrated Circuits Conference (CICC), pp. 729 – 732, September 2008.  M.C. Kuo, S.W. Kao, C.H. Chen, T.S. Hung, Y.S. Shih, T.Y. Yang, and C.N. Kuo “A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13μm CMOS,” IEEE Journal of Solid-State Circuits, Vol.44, pp. 740 – 750, March 2009.  D.H. Lee, H. Jeonghu, P. Changkun, and H. Songcheo, “A CMOS Active Balun Using Bond Wire Inductors and a Gain Boosting Technique,” Microwave and Wireless Components Letters, Vol.17, pp. 676 – 678, September 2007.  S.C. Blaakmeer, E.A.M. Klumperink, D.M.W. Leenaerts, and B. Nauta, “Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling,” IEEE Journal of Solid-State Circuits, Vol.43, pp. 1341 – 1350, June 2008.  S.C. Blaakmeer, E. Klumperink, D.M.W. Leenaerts, B. Nauta, “The Blixer a Wideband Balun-LNA-I/Q-Mixer Topology,” IEEE Journal of Solid-State Circuits, Vol.43, pp. 2706 – 2715, December 2008.  D.V. Kien, Choi, G. Byoung, and P.C. Soon, “ A Dual-band CMOS RF Front-end for 2.4/5.2 GHz Applications,” IEEE Radio and Wireless Symposium, pp. 145 – 148, June 2007.  S.S. Mehta, D. Weber, M. Terrovitis, K. Onodera, M.P. Mack, B.J. Kaczynski, H. Samavati, S.H.-M. Jen, W.W. Si, Lee MeeLan, K. Singh, S. Mendis, P.J. Husted, Ning Zhang, B. McFarland, D.K. Su, T.H. Meng, and B.A. Wooley, “An 802.11g WLAN SoC,” IEEE Journal of Solid-State Circuits, Vol.40, pp. 2483 – 2491, December 2005.  M. Zargari, M. Terrovitis, S.H.M. Jen, B.J. Kaczynski, M. Lee, M.P. Mack, S.S. Mehta, S. Mendis, K. Onodera, H. Samavati, W.W. Si, K. Singh, A. Tabatabaei, D. Weber, D.K. Su, and B.A. Wooley, “A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN,” IEEE Journal of Solid-State Circuits, Vol.39, pp. 2239 – 2249, December 2004.  C. F. Liao, and S. I. Liu, “A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers,” IEEE Journal of Solid-State Circuits, Vol.42, pp. 329 – 339, February 2007.  W.C. Huang , C.M. Hsu, C.M. Lee, H.Y. Huang, and C.H. Luo, “Dual band LNA/mixer using conjugate matching for implantable biotelemetry,” ISCAS Symposium, pp. 1764 – 1767, May 2008.  Z. Li, R. Quintal, and K.K. O, “A dual-band CMOS front-end with two gain modes for wireless LAN applications,” IEEE Journal of Solid-State Circuits, Vol.39, pp. 2069 – 2073, November 2004.  R.R. Kishor, J. Wilson, and M. Ismail, “A CMOS RF front-end for a multistandard WLAN receiver,” Microwave and Wireless Components Letters, Vol.15, pp. 321 – 323, May 2005.  B. Razavi, “RF Microelectronics,” Prentice Hall, 1997。  D.M. Pozar，微波工程，高立圖書，民國95年4月。  B. Razavi，類比CMOS積體電路設計，滄海書局，民國97年三月。  D-Link技術團隊, “無線區域網路技術白皮書,” 松崗, 2005。||摘要:||
第二章的內容為低雜訊放大器設計。在此我們分析雜訊特性並且運用雜訊抑制的技巧設計一組雙頻帶低雜訊放大器。此電路使用TSMC 0.18 m CMOS製程製作。使用SB封裝並於PCB板量測情況底下，2.4GHz與4.7GHz量得之雜訊指數分別是4.4dB與4.6dB；功率增益則分別為9.3dB與11.2dB。此電路於1.8V偏壓下的直流功率消耗為16mW。
第三章為雙頻帶直接降頻混波器，分別使用TSMC 0.35 m SiGe BiCMOS製程及TSMC 0.18 m CMOS製程各完成一顆晶片。SiGe製程製作之晶片直接降頻至50MHz，量測結果雜訊指數20dB以下，功率轉換增益約5dB。此電路之功率轉換增益與線性度為近乎平衡的設計，以外並有良好隔離度。在3V操作電壓下，直流功率損耗為6mW。另一顆使用0.18 m CMOS製程設計之混波器亦降頻至50MHz，量得之雜訊指數約20dB，轉換增益約2dB；在1.8V操作電壓下，直流功率損耗為3.5mW。
第四章為應用於雙頻帶接收機之射頻前端電路，包含低雜訊放大器，主動巴倫電路，直接降頻混波器。此電路使用TSMC 0.18 m CMOS製程，於功率損耗25mW情況下，完成直接降頻50MHz，雙頻帶雜訊指數4dB以下，轉換增益於20dB以上，線性度高於-30dBm之模擬設計。
This thesis presents the receiver RFIC design for WLAN 802.11a/b/g dual band application using noise reduction technique in circuit design and system conception. This thesis is composed of three parts: low noise amplifiers (LNA), mixers, and the complete receiver front end. In each part, the content includes the circuit design, system analysis, chip measurement results, and a short discussion.
In chapter two, a LNA using noise reduction technique of dual band application which is implemented in TSMC 0.18 m process technology is presented. The on-bond measured NF for the proposed dual band LNA with SB package are 4.5dB and 6.8dB at frequencies 2.4GHz and 4.7GHz, respectively. The measured power gains are 9.3dB and 11.2dB at frequencies 2.4GHz and 4.7GHz, respectively. The power consumption of the proposed LNA is 16mW under 1.8V voltage supply.
In chapter three, a first mixer of direct down conversion system for dual band application is implemented in TSMC 0.35 m SiGe BiCMOS process technology. The on-wafer measured NF for the mixer of the dual band system is smaller than 20dB with IF at 50MHz. The power conversion gain is near 5dB at dual band of direct down conversion system. The measured data show good isolations and balance between linearity and power conversion gain. The dc power consumption is 6mW under 3V voltage supply. On the other hand, the second mixer of direct down conversion system for dual band application is implemented in TSMC 0.18 m CMOS process technology. The on-wafer measured NF for the mixer is smaller than 20dB with IF at 50MHz. The power conversion gain is near 2dB. The mixer consumes 3.5mW power from a 1.8V voltage supply.
In chapter four, a complete direct down conversion receiver RF front end for dual band application is presented. This circuit includes a dual band LNA, active balun circuits, and a direct conversion mixer, and it is designed in TSMC 0.18 m process technology. The front-end simulated NF is smaller than 4dB at dual band. The power conversion gain is more 20dB. The total power consumption is 25mW under 1.8V voltage supply.
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