Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8840
標題: 應用於窄頻電力線通訊之直接序列展頻數據機設計與實現
Design and Implementation of A DSSS-Based Narrow Band Power Line Communication Modem
作者: 張峰銘
Chang, Feng-Ming
關鍵字: Narrowband PLC;窄頻電力線通訊;DSSS;MBOK;FSK;transition counting technique;直接序列展頻;M路雙正交調變;頻率鍵移;轉態計數技術
出版社: 電機工程學系所
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摘要: 
使用電力線作為通訊媒介在許多應用上,提供一個便利又低成本的解決之道,因為電力網存取方便且覆蓋率為全球最廣闊。在本論文中,我們針對「智慧型室內電力監控系統」,設計出一個低複雜度的電力線通訊數據機,調變機制含有兩個階段,分別為作為直接序列展頻的M路雙正交鍵移,還有頻率鍵移。在M路雙正交鍵移的階段,使用修正型華氏碼來降低傳統型華氏碼的自性關性函數之旁葉,同時提供更好的偵測效果,模擬結果也呈現它相較於傳統型華氏碼明顯改善了效能,其在封包偵測與時序還原電路的議題上,因為無需昂貴的數位/類比轉換器,所以硬體複雜度更加減少且維持低成本,另外正、負雙緣偵測的策略可以達到雙倍取樣之效果,在頻率鍵移的階段,則利用簡單的轉態計數技術,這種低複雜度的技術很適合講求價廉的一般家庭應用。我們提出的數據機能夠在400kHz的頻寬內達到傳輸速率100kbps,而且也提供了足夠強健的通訊協定與主僕式網路架構。

除了電力線通訊數據機以外,本論文中也建立了電力線通訊的通道模型,衡量了有色背景雜訊、窄頻雜訊、脈衝雜訊三種雜訊型態,根據發展出的通道模型,可以進行位元錯誤率的模擬,然後有效地驗證我們所提出的電力線通訊之調變方法。

最後,具有8位元PicoBlaze微處理器的基頻電力線通訊數據機在Xilinx FPGA (Field Programmable Gate Array)上實現,還發展了涵蓋一個主控端與三個僕節點的電力線通訊之測試網路。

Due to the readiness and extensive coverage of power networks, using power-lines as communication media provides a convenient and cost-effective solution for data transmission in many applications. In this thesis, a low complexity power-line modem design targeting intelligent in-house power monitor and control system is presented. The adopted modulation scheme is a combination of the M-ary Bi-Orthogonal Keying (MBOK) for Direct Sequence Spread Spectrum (DSSS) followed by the Frequency Shift Keying (FSK). In MBOK modulation, modified Walsh codes are employed to reduce the sidelobes of the auto-correlation for better detection. Simulation results also indicate significant performance enhancement against using conventional Walsh codes. The detection and clock timing recovery circuitry are hardware-efficient requiring no expensive D/A converters. A dual edge detection policy is adopted to effectively double the timing resolution. In the FSK modulation stage, the demodulation scheme is accomplished by using a simple transition counting technique. This gives rise to a low complexity design suitable for the cheap deployment in the household. The proposed modem is capable of delivering a data rate up to 100kbps over a 400kHz channel. It also supports a robust communication protocol and a network using master-slave configuration.

Besides the PLC modem design, a power line communication model is also developed in this thesis. Three types of noises, i.e. colored noise, narrowband noise and impulse noise, are modeled. Based on the developed channel model, BER simulations are conducted to verify the effectiveness of the proposed PLC modulation scheme.

Finally, the baseband PLC modem design equipped with an 8-bit PicoBlaze embedded processor has been implemented in a Xilinx FPGA (Field Programmable Gate Array). A trial control network incorporating one master and three slave nodes to demonstrate the power line communication is also developed.
URI: http://hdl.handle.net/11455/8840
其他識別: U0005-1612201015044000
Appears in Collections:電機工程學系所

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