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標題: | 應用於高傳輸量光纖通訊系統之結合RS和LDPC解碼器VLSI實作 VLSI implementation of high throughput combined RS and LDPC decoders for optical communications |

作者: | 姚長昆 Yao, Chang-Kun |

關鍵字: | LDPC;低密度同位元查核碼;RS;Reed-Solomon;VLSI;optical;里德索羅門碼 |

出版社: | 電機工程學系所 |

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摘要: | 本論文提出應用於高傳輸量光纖通訊系統之結合RS和LDPC解碼器VLSI實作。在本論文有四個主要的重點：(1).建構分割轉移LDPC Code (Partition and Shift LDPC, PS-LDPC)，此PS-LDPC (2550,2040) 是一種規則式的查核矩陣，行權重和列權重分別為3和15，碼率為4/5，其編碼前的資料長度和RS (255,239)編碼後的資料長度一樣，以利硬體實現。(2).提出改善LLR數值量化的方式來達到更好的效能，此Modified LLR的方法並不會影響LDPC的解碼架構。(3).提出2 bits Modified Layered Min Sum Algorithm (2M-LMSA)來減少查核點單元的運算量。(4).提出的RS解碼器和LDPC解碼器在解碼步驟能匹配使用，不造成電路閒置的情形。 本論文RS解碼器的演算法架構使用recursive degree computationless Modified Euclidean Algorithm (rDcMEA)，其解碼的潛伏期為(2t)2 +4個clocks。而在每個RS解碼步驟區塊，設計成288 clocks完成其解碼步驟。在使用UMC 90nm CMOS製程下，其RS解碼器經由電路合成動作後，面積為0.19mm2，而頻率可達714 MHz. LDPC解碼器的架構為雙路徑部分平行式架構，使用的演算法是本論文所提出減少查核點運算的2M-LMSA，每個區塊解碼需96個clocks解碼。本論文整合RS解碼器和LDPC解碼器的使用，在使用UMC 90nm CMOS製程下，RS&LDPC 解碼器可達到在頻率208MHz下，傳輸量為11Gb/s，其核心電路面積為3.45 mm2，而在供應電壓為0.9V下，平均功率消耗為434mW。 In this thesis, VLSI Implementation of high throughput combined RS and LDPC decoders for optical communications is presented with four major objects. The first is constructing a Partition and Shift LDPC Code (PS-LDPC Code). The PS-LDPC (2550, 2040) check matrix is a regular check matrix in which the column weight and row weight are 3 and 15, respectively, with the coding rate of 4/5. The data length of PS-LDPC Code before encoding is the same as the codeword length of RS (255,239) after encoding. Secondly, a modified quantization of likelihood ratio called Modified LLR is proposed to improve the performance. It does not influence the LDPC decoder architecture. The next is the 2 bits modified layered min sum algorithm called 2M-LMSA, which can reduce check node computation complexity. Finally, by appropriate architecture design, the decoding latencies of the RS and LDPC decoders are matched well to avoid idleness. The RS decoder architecture utilizes recursive degree computationless modified Euclidean Algorithm (rDcMEA) with decoding latency of (2t)2 +4. The total clock cycles are 288 per RS decoding blocks. The RS decoder was designed and implemented using UMC 90nm CMOS technology. The synthesized result shows that the proposed RS (255,239) decoder only occupies about 0.19 mm2 at clock rate of 714MHz. The LDPC decoder employs a dual path partial parallel architecture using the proposed 2M-LMSA to reduce check node unit (CNU) computation complexity. The total numbers clock cycles are 96 per LDPC decoding blocks. The combined RS and LDPC decoders called RS&LDPC decoder was designed and implemented using UMC 90nm CMOS technology. The RS&LDPC decoder can achieve the decoding throughput of 11Gb/s at the clock frequency of 208 MHz after auto place route (APR) . The average power consumption is 434mW at supply voltage of 0.9 V with the core area of 3.45 mm2. |

URI: | http://hdl.handle.net/11455/8885 |

其他識別: | U0005-2107201012252100 |

Appears in Collections: | 電機工程學系所 |

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