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dc.contributorMing-Hua Shuien_US
dc.contributorChen-Hao Changen_US
dc.contributor.advisorHong-Chin Linen_US
dc.contributor.authorWu, Chien-Chengen_US
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K. T. Mok, “A CMOS Voltage Reference Based on Weighted △VGS for CMOS Low-Dropout Linear Regulators,” IEEE J. Solid-State Circuits, vol. 38, pp.146-150, Jan. 2003. [15] Chia-Wei Chang; Tien-Yu Lo; Chia-Min Chen; Kuo-His Wu; Chung-Chih Hung; “A Low-Power CMOS Voltage Reference Circuit Based on Subthreshold Operation” IEEE International Circuit Symp. Circuits and Systems (ISCAS), 2007, pp. 3844-3847. [16] G. De Vita and G. Iannaccone “A Sub-1-V, 10ppm/ oC, Nanopower Voltage Reference Generator,” IEEE J. Solid-State Circuits, vol.42, pp.1526-1542, July 2007. [17] Yongjia Li; Xiaojuan Xia; Weifeng Sun; Shengli Lu; “A 760mV CMOS Voltage Reference With Mobility and Subthreshold Slope Compensation” IEEE International Conference on ASIC, 2009, pp.1145-1148. [18] G. De Vita and G. Iannaccone, and P. Andrani, “A 300nW,12ppm/oC Voltage reference in a digital 0.35μm CMOS process” Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 81-82. [19] “Technical Review of Low Dropout Voltage Regulator Operation and Performance,” Application Report, Texas Instruments, Aug.1999 [20] M. Layachi & Y. Chouia, “Low Dropout Voltage Regulaotr,” Department of Electrical Engineering, Ecole Polytechnique de Montreal. [21] K.C. Kwok and P.K.T. Mok, “Pole-Zero Tracking Frequency Compensation For Low Dropout Regulator,” IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, USA Vol. IV, pp. 735-738, May 2002. [22] 黃志揚, “低壓降線性穩壓器頻率補償之改善方法,” 2004年碩士論文, 國立清華大學 [23] S. Szczepanski, J. Jakusz, and R. Schaumann, “A linear fully balanced CMOS OTA for VHF filterfing Applications” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Proc, vol. 44 pp.174-187, Mar. 1997. [24] Airong Liu and Huazhong Yang, “Low Voltage Low Power Class-AB OTA with Negative Resistance Load,” International Conference on Communications Circuits and Systems, pp. 2251-2254, June 2006. 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[29] Huang, W.-J. ; Liu, S.-I. ; “Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array,” IET Circuit, Devices & Systems , pp. 306-316, 2008. [30] O. Khouri, R. Micheloni, S. Gregori, and G. Torelli, “Fast Voltage Regulator for Multilevel Flash Memories,” in Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing, pp.34-38, Aug.2 [31] A. Maity, R. G. Raghavendra, and P. Mandal, “On-chip Voltage Regulator with Improved Transient Response,” in Proceedings of the 18th International Conference on VLSI Design, pp. 522-527, 2005.zh_TW
dc.description.abstract近年來,由於積體電路技術日益成熟,可攜式電子產品也愈來愈多。在可攜式產品裡,講求的是體積小、外觀精美、功能強大,所以在積體電路上,也朝著低功耗來發展。 在參考電壓電路的應用上,種類繁多如:D/A、A/D轉換器及穩壓器等,皆需要參考電壓電路提供一個有效且準確的參考電壓值,在本論文中,提出了一個具溫度漂移校準之純CMOS參考電壓電路,可以在晶片完成後,經由其中的開關調微調其溫度係數,且保留了低操作電壓、低功耗、不受溫度影響及晶片面積小等優勢。此電路使用的是TSMC 0.18μm CMOS製程,下線後的量測結果顯示,其消耗功率為74nW,溫度係數經調整後為6.7ppm/oC,晶片積為0.0076mm2。 傳統的LDO穩壓電路,需要一個很大的外部電容(數μF),以維持電路的負回授穩定,但在積體電路裡,即使是nF的電容都是占用昂貴的晶片面積,也不符合成本。在本論文裡另一個主題為設計一個不需外部電容的線性穩壓器(cap-free LDO),此LDO採用的是3級的放大器設計,使用窩巢式米勒補償方式,可以將電路看成一個單一極點的電路使其達到穩定。使用的是TSMC 0.35μm CMOS製程,其設計的最大負載電流為150mA,從模擬結果顯示,輸出電壓為2.5V及3.3V時,輸入電壓分別為2.8V~5V 與3.3V~5V,其Dropout Voltage為300mV,靜態電流為96μA。在無外在電容時,且在最差的情形下,undershoot voltage為220mV,overshoot voltage為206mV。zh_TW
dc.description.abstractIn recent years, integrated circuit technology becomes more sophisticated, so more and more portable electronic products appear in our daily lives. The portable products require small sizes, nice looking, and multi-functions. Therefore, integrated circuits tend to very low power consumption. In applications of the reference voltage circuits, many circuits such as: D/A, A/D converters, voltage regulators, etc., require a reference voltage circuit to provide the accurate reference voltage effectively. In this paper, we propose a low-voltage, low-power pure CMOS voltage reference circuit on very small area with temperature drift calibration. This circuit was fabricated on area of 0.0076mm2 using TSMC 0.18μm CMOS process. The measurement results reveal that the power consumption is 74nW, with temperature coefficient of 6.7ppm/oC after calibration. The conventional LDO voltage regulators require a large external capacitor (a few μF) in order to maintain stability due to negative feedback. However, in the integrated circuits, even the nF capacitor occupies very large chip area, which is not cost effective. Another goal in this thesis is to design a linear regulator without external capacitors (cap-free LDO). The LDO utilizes a three-stage amplifier with nested Miller compensation. The circuit may be equivalent to a single pole circuit for stability. The proposed circuit was designed using TSMC 0.35μm CMOS process for the maximum load current of 150mA. The simulation results show that input voltages are 2.8V ~ 5V and 3.3V ~ 5V for the output voltage of 2.5V and 3.3V, respectively. The dropout voltage is 300mV, and the quiescent current is 96μA. For the worst case without external capacitors, the undershoot voltage is 220mV and the overshoot voltage is 206mV.en_US
dc.description.tableofcontents誌謝 i 中文摘要 ii 英文摘要 iii 目錄 iv 圖表目錄 vi 第一章 序論 1 1.1 研究動機 1 1.2 參考電壓電路的應用 3 1.2.1數位類比轉換器(D/A converter) 3 1.2.2類比數位轉換器(A/D converter) 3 1.2.3電壓偵測電路(Voltage detector) 4 第二章 參考電壓電路介紹 5 2.1 傳統的能隙參考電壓設計 5 2.1.1雙載子電晶體二極體連接之溫度特性 5 2.1.2 PTAT產生器 6 2.1.3 Kujik能隙參考電壓電路 8 2.2可操作於1V以下的能隙參考電壓電路 11 2.3利用閘-源極電壓差的參考電壓電路 12 2.4運用次臨界區之參考電壓電路 14 2.5 操作於1伏特以下低功率之參考電壓電路 16 第三章 具溫度漂移校準之純CMOS參考電壓電路 18 3.1電流源產生器(Current Generator) 18 3.2啟動電路(Start-Up) 20 3.3溫度可校準的參考電壓核心電路 21 3.3.1最小操作電壓範圍 25 3.3.2 Hi-V NMOS與標準NMOS的Vth對溫度關係 25 3.4Unity-Gain Buffer 28 3.5模擬結果與電路佈局 29 3.5.1參考電壓對供應電壓的敏感度 29 3.5.2製程變異對參考電壓的影響 29 3.5.3參考電壓在不同情形下對溫度的變化 30 3.5.4參考電壓的PSRR 32 3.6量測結果與電路佈局 34 3.6.1量測方法與結果 34 3.6.2電路佈局及晶片照相圖 35 3.7效能與比較 38 第四章 低壓降線性穩壓器(LDO)簡介 39 4.1低壓降線性穩壓器(LDO) 39 4.2LDO的重要參數定義 40 4.2.1壓降電壓(Dropout Voltage) 40 4.2.2靜態電流(Quiescent Current) 40 4.2.3電源效率(Power Efficiency) 41 4.2.4負載調節率(Load Regulation) 41 4.2.5線性調節率(Line Regulation) 42 4.2.6暫態響應(Transient Response) 43 4.2.7頻率響應(Frequency Response) 45 4.2.8穩定度與輸出等效串接電阻範圍(Range of Stable ESR) 46 4.2.9輸出準確率(Output Accuracy) 47 4.2.10傳輸電晶體(Pass Transistor)種類 47 4.3穩定度與頻率補償 49 4.3.1極零點補償法 49 4.3.2追蹤零點補償法 50 第五章 改良式無外部電容之LDO穩壓器 52 5.1改良式傳統偏壓電路 53 5.2誤差放大器 55 5.3Capacitor-Free LDO 59 5.4加入放電路徑的Cappacitor-Free LDO 64 5.5模擬結果與電路佈局 66 5.6效能與比較 75 第六章 結論與未來工作 76 參考文獻 77zh_TW
dc.titleA Pure CMOS Voltage Reference Circuit with Temperature Drift Calibration and an Improved Capacitor-Free Low Dropout Regulatoren_US
dc.typeThesis and Dissertationzh_TW
item.openairetypeThesis and Dissertation-
item.fulltextno fulltext-
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