Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8929
標題: 應用於HDTV1080p之H.264/AVC高級規範幀內畫面編碼器之快速演算法研究及其電路架構設計與實現
Fast Algorithm and Architecture Design of H.264/AVC High Profile Intra Frame Coder for HDTV1080p Applications
作者: 王偲帆
Wang, Sz-Fan
關鍵字: H.264/AVC;H.264/AVC;intra frame coder;fast algorithm;high profile;幀內畫面編碼;快速演算法;高級規範
出版社: 電機工程學系所
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Fan, “Fast 2-Dimensional 4×4 Forward Integer Transform Implementation for H.264/AVC,” IEEE Trans. Circuit and System, vol. 53, no. 3, pp. 174-177,Mar. 2006. [26] H. Qi, W. Gao, S. Ma, and D. Zhao, “Adaptive Block-Size Transform Based on Extended Integer 8×8/4×4 transform s for H.264/AVC,” IEEE International Conf. on Image Processing, pp. 1341-1344, Oct. 2006. [27] T. C. Wang, Y. W. Huang, H. C. Fang, and L. G. Chen, “Parallel 4×4 2D Transform and Inverse Transform Architecture for MPEG-4 AVC/H.264,“ in Proc. IEEE ISCAS. May 2003, pp. 800-803. [28] Y. C. Chao, S. T. Wei, J. F. Yang, and B. D. Liu, “Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders,“ IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007. [29] K. H. Chen, J. I. Guo, Member, and J. S. Wang, Member, “A High-Performance Direct 2-D Transform Coding IP Design for MPEG-4 AVC/H.264” IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 4, April 2006. [30] Rahman C. A., and Badawy W., “An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder,” in proc. SIPS' 06, page(s):368 - 371, Oct. 2006. [31] D. Kim, E. Jung, H. Park, H. Shin, and D. Har, “Implementation of High Performance CAVLC for H.264/AVC Video Coding,” in Proc. The 6th International Workshop on System-on-Chip for Real-Time Applications, page(s):20 - 23, Dec. 2006. [32] Rahman C. A., and Badawy W., “CAVLC Encoder Design for Real-Time Mobile Video Applications,” in Proc. TCSII' 07, vol. 54, page(s):873 - 877, Oct. 2007. [33] T. C. Chen, Y. W. Huang, C. Y. Tsai, B. Y. Hsieh, and L. G.. Chen, “Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile,” in Proc. of IEEE VLSI-TSA Int. Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), 2005. [34] C.Y. Tsai, T. C. Chen, and L. G. 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摘要: 
幀內畫面編碼主要用於影像壓縮中的任務是解決單張畫面上空間的冗餘,而H.264/AVC中的幀內畫面編碼則是採用邊界形成的各種預測方向進行預測並找尋最佳預測模式;在幀內畫面編碼的預測模式中,我們使用兩種快速演算法,其一是在I4MB預測模式使用三方向性三步演算法,減少最佳模式判斷錯誤機率以增加畫面品質,並與修改版三步演算法所需運算模式數量相同;同時I8MB預測模式數量從九種預測模式變成最多四種預測模式,藉由減少預測模式的數量來減少所需要運算的時間,以達到降低工作頻率的目的。
硬體架構方面,為配合I8MB預測模式所需要的邊界,我們重新規畫了幀內預測畫面產生器的排程,提高其運算資料的使用率,並且利用新規畫的排程,安插I8MB預測模式所需要的邊界並產生I8MB預測時所需要預測畫面,因此不論I8MB預測模式中所需預測的模式為何,不需要額外的硬體即可立即產生其所需的預測畫面,同時我們的架構亦能處理I16MB平面模式的預測。採用單一核心之多重轉換架構,可以同時產生整數轉換和Hadamard轉換的結果,來達到減少執行週期與維持影像品質模式,模式預測時採用的是經過Hadamard轉換後的相減轉換絕對值之和(Sum Of Absolute Transformed Differences)值,如此跟幀間預測的成本才會相同,減少預測錯誤的發生而得到最佳的預測模式決定。
我們提出規格為每秒30張畫面FullHD 1080p解析度,以8點像素平行度的H.264/AVC高級規範幀內畫面預測與編碼架構電路,其運作頻率為155 MHz,若此電路運作於HD 720p@30fps的規範,則僅需68.1 MHz內即可完成。

In this thesis, we proposed two fast intra prediction algorithms for 4×4 intra prediction (I4MB) and 8×8 intra prediction (I8MB) respectively. The proposed I4MB fast algorithm utilizes Three-Directional Three-Step algorithm to improve the rate-distortion algorithm and to reduce the intra prediction modes. For I8MB, only four prediction modes at most are performed to reduce the computational complexity.
In the light of our fast algorithms, we propose a novel data scheduling to improve the hardware utilization. We also utilize the proposed multi-transform architecture with unified kernel to perform the integer transform and the sum of absolute transformed difference (SATD) value simultaneously.
The implementation result shows that the proposed architecture can achieve H.264/AVC high profile (HP) HD720p and HD1080p intra coding in real-time at 68.1MHz and 155MHz respectively by using UMC 0.09μm 1P9M CMOS process.
URI: http://hdl.handle.net/11455/8929
其他識別: U0005-2308201015124400
Appears in Collections:電機工程學系所

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