Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8949
標題: 應用於平面顯示器之低偏移電壓緩衝放大器
Low-Offset Buffer Amplifier for FPD Applications
作者: 劉政杰
Liu , Cheng-Chieh
關鍵字: buffer amplifier;緩衝放大器;rail to rail;low-offset;軌對軌;低偏移電壓
出版社: 電機工程學系所
引用: [1] 汪芳興,“非晶矽薄膜電晶體液晶顯示器驅動電路積體電路技術”,電子月刊, 頁數:98-108, 2003 年8 月。 [2] 戴亞翔, TFT-LCD 面板的驅動與設計, 五南圖書出版, 民國95 年4月。 [3] 林振華, MOS類比電路, 全華科技圖書出版, 民國89 年1月。 [4] Behzad Razavi, Design of Analog CMOS Integrated Circuit, New York:McGRAW- HILL, 2001. [5] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, NewYork: Oxford, 2002. [6] R. Hogervorst and J. H. Huijsing, Design of Low-Voltage, Low-power Operational Amplifier Cells, Kluwer Academic Publishers, 1999, pp.23-31. [7] S. Sakurai and M. Ismail, Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation, Kluwer Academic Publishers, 1995 [8] Guo-Teng Hong and Chih-Hsiung Shen, Low Offset High Voltage Swing Rail-to-Rail Buffer Amplifier for LCD Driver, IEEE Conference Electron Devices and Solid-State Circuits, 2007. EDSSC 2007, 20-22 Dec. 2007 Page(s):841 - 846 [9] C.-W. Lu, High-Speed Driving Scheme and Compact High-Speed Low-Power Rail-to-Rail Class-B Buffer Amplifier for LCD Applications, IEEE J. Solid-State Circuits, 2004, pp. 1938-1947. [10] T.-H. Hsu and F.-H. Wang, A High slew rate and low offset voltage buffer for TFT-LCD source driver, SID 2006, pp. 333-335. [11] S.-K. Kim, Y.-S. Son, Y.-J. Jeon, Low-power High-slew-rate CMOS Buffer Amplifier for Flat Panel Display Drivers, SID 2006, pp. 336-338. [12] M.-D. Ker, C.-K. Deng, and J.-L. Huang, On-Panel Design Technique of Threshold Voltage Compensation for Output Buffer in LTPS Technology, SID 2005, pp. 288-291. [13] Tetsuro Itaku, Hironori Minamizaki, Tetsuya Satio, and Tadashi Kuroda, “A 402-Output TFT-LCD Driver IC With Power Control Based on the Number of Colors Selected,” IEEE Journal of Solid-State Circuits, Vol. 38, No.3, March, pp. 503-510, 2003. [14] P. K. Chan, L. Siek, H.C. Tay, J.H. Su, A Low-Offset Class-AB CMOS Operational Amplifier, ISCAS 2000, pp. 455-458.
摘要: 
本論文設計一應用於液晶平面顯示器上之電壓緩衝器。所設計之電路其製程為TSMC 0.35μm 2P4M CMOS 3.3V供應電壓之製程,製作兩種不同的緩衝放大電路。第一種緩衝放大電路為軌對軌輸出之緩衝放大器,有偏壓電路部份,及互補式摺疊疊接差動輸入對以及使用Class AB作為輸出級,使得電路輸入與輸出範圍可由0.02V ~3.301V具有軌對軌之特性。所設計之電壓緩衝器之上升時間為0.183 μs、下降時間0.18 μs及上升穩定時間(±0.2%)為2.23 μs、下降穩定時間(±0.2%)為2.96 μs。開迴路增益74 dB、相位邊限85°,電路面積約是28 x 177 μm2。

第二種緩衝放大電路為低偏移電壓之緩衝放大器,電路偏壓部分是採用穩定性佳且不受外在因素影響的疊接電流源作為偏壓電路,使得緩衝器的偏移電壓值為5.21mV,其架構為Bias偏壓電路,兩級增益放大器,最後為一個輸出級,其上升時間為36.6ns、下降時間(±0.2%)30.1ns及上升穩定時間(±0.2%)為0.891 μs、下降穩定時間(±0.2%)為0.898 μs。相位邊限72°及平均偏移電壓(offset voltage)僅約0.6 mV(0.5V~2.8V),最大偏移電壓(offset voltage) 5.2mV(2.8V~3.204V),電路面積約為44 x 110 μm2。
URI: http://hdl.handle.net/11455/8949
其他識別: U0005-2608201000432900
Appears in Collections:電機工程學系所

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