Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8959
標題: LC-Tank振盪器相位雜訊與消耗功率設計之權衡與寬頻注入鎖定除頻器
Design of LC-tank Oscillators to Comprise Phase Noise and Power Consumption and Dividers with Wide Locking Range
作者: 傅冠霖
Fu, Guan-Lin
關鍵字: Phase Noise;相位雜訊;Oscillators;Dividers;振盪器;除頻器
出版社: 電機工程學系所
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摘要: 
本論文有四個主題,第一個主題為研究壓控振盪器之LC-tank最佳化設計為主題,將探討壓控振盪器高頻與低頻時,電感L與電容C之選取,在低頻時以等效電導Gequi與相位雜訊等效電阻Reff此兩複合參數為基礎得出一個權衡設計方案,且以TSMC 0.18 um製程完成晶片製作,量測範圍為8.3 GHz至9.63 GHz,相位雜訊在1MHz偏移量為-115dBc/Hz,消耗功率為14.76 mW。
第二個主題主要設計兩個壓控振盪器,第一個使用振幅偵測器,降低起振條件,達到低消耗功率,以TSMC 0.18 um 製程完成晶片製作,操作頻率為24 GHz,相位雜訊在1MHz偏移量為-105dBc/Hz,消耗功率為11 mW。第二個壓控振盪器使用放大器抵銷LC-tank的損耗,使用電感串聯可變電容增加整體被動網路的輸入阻抗,隔絕可變電容與電晶體寄生電容之影響,降低起振條件,達到降低消耗功率並操作在較高頻率之設計,使用變壓器設計減少面積與增加可調範圍。
第三個主題本主要設計注入鎖定除二除頻器,使用電阻並聯架構,降低LC-tank的Q值,增加除頻範圍,使用currrent bleeding架構解決降低Q值所造成之功率消耗影響,但降低除頻範圍,最後改良使用增大注入鎖定技術同時解決除頻範圍與降低消耗功率,以TSMC 0.18 um製程完成晶片製作,量測輸入頻率為11.9 GHz至18 GHz,除頻範圍為40.8%,消耗功率為4.4mW。
最後一個主題主要設計注入鎖定除三除頻器,第一個除三除頻器由混頻器和注入鎖定除二除頻器所構成,使用直接注入鎖定架構降低消耗功率,使用電感濾波架構增加鎖定除頻範圍,TSMC 0.18 um製程完成晶片製作,量測操作頻率為9.2 GHz至12.3 GHz,操作範圍為29 %,消耗功率為10.8 mW。第二個除三除頻器由混頻器、放大器與注入鎖定除二除頻器所構成,為了解決混頻器輸出功率過小的問題,使用放大器放大混頻器輸出訊號並使用注入鎖定放大技術,提升整體輸出功率,以增加除頻鎖定範圍,量測操作頻率為18.4 GHz至21.9 GHz,注入鎖定除頻範圍為17%,消耗功率為19 mW。

This thesis includes four topics, the first topic focus on the optimization of LC-tank in voltage control oscillator , we discuss the selection of inductance and capacitance for high and low frequency application. The approach uses both parameters such as effective conductance and effective resistance,to compromise the phase noise and power consumption. Measurement show tuning range 8.3GHz to 9.63GHz , phase noise is -115dBc/Hz at 1MHz offset, power consumption is 14.76mW.
The second topic implements two voltage control oscillators ,the first one uses amplitude detector to reduce the power consumption, operated at 24GHz, phase noise -105dBc/Hz at 1MHz offset, using TSMC 0.18um process to fabricate the chip. The second one uses amplifier to cancel the loss of LC-tank and use the series connection of inductor and varactor to increase input impedance and isolate the parasitic capacitances of varactor and transistor, decrease the power consumption and operation in more higher frequency, also uses transformer to reduce chip area.
The third topic describes 2:1 injection-locked frequency dividers, the proposed topology used parallel resistance to reduce quality factor of LC-tank, uses current bleeding approach to decrease power consumption. However, the topology disadvantage reduces the locking range. The improvement circuit adopts double injection-locked approach, increases locking range and decrease power consumption. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 11.9 GHz to 18 GHz, the locking range is 40.8%,power consumption is 4.4 mW.
The last topic describes 3:1 injection-locked frequency dividers ,the first one adopts a mixer and a 2:1 injection-locked frequency dividers to decrease power consumption and connet and inductor to cancel parasitic capacitances to increase locking range. The measured operation frequency is from 9.2 GHz to 12.3 GHz, the operation range is 29%,power consumption is 10.8mW.The second circuit to solve the low output power an amplifier is used enlarge output signal and from enhance output power. The measure frequency is from 18.4 GHz to 21.9 GHz, the locking range is 17%,power consumption is 19mW.
URI: http://hdl.handle.net/11455/8959
其他識別: U0005-2701201116074200
Appears in Collections:電機工程學系所

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