Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8978
標題: 低複雜度且低功率之雙緣觸發型正反器與預除器
Low Complexity and Low Power Designs on Double-Edge-Triggered Flip Flop and Prescaler
作者: 陳守偉
Chen, Shou-Wei
關鍵字: 通過式邏輯;PTL;正反器;預除器;flip-flop;prescaler
出版社: 電機工程學系所
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摘要: 
在本篇論文中分別提出兩種改良型的電路;第一種為雙緣脈波觸發型正反器(Double-Edge-Triggered Flip-Flop),電路中利用簡易的設計成功的解決傳統通過式邏輯(PTL:Pass-Transistor Logic)電路所造成臨界電壓衰退的問題(Threshold Voltage Loss)。所提出的雙緣脈波產生器,利用內部節點產生的訊號,加上一個電晶體nMOS,使得原本的缺點得以解決。本雙緣脈波觸發型正反器(Double-Edge-Triggered Flip-Flop)之電路設計包含了一XOR邏輯模組之脈波產生器(Pulse Generator)以及一準位式栓鎖器(Level sensitive latch)。整體性能比較的電路為ep-SFF、ep-DSFF及XNOR-PFF。與最佳設計比較,在延遲時間方面,我們所提出的設計提升了12.5%,同時平均功率消耗部分亦節省15%。
第二種電路為一個新型的除2/3預除器,其優點為擁有較低的功率消耗、更高的工作頻率。在除2/3預除器的電路中,傳統的設計方法是將額外的邏輯閘與正反器做整合,來達到能夠工作在更高操作速度的目的。在此,我們提出一個基於E-TSPC架構的新式低功率除2/3預除器,且僅僅需要13個電晶體就能完成電路;在使用PTL電路技巧後,不僅能將整體的電晶體數目減低,更能將額外的邏輯閘從關鍵路徑中移除,而與傳統電路相較,所提出的除2/3預除器的操作速度提升了12.2%,而功率延遲乘積(PDP:Power-Delay-Product)節省23.4%。
最後,本論文中電路設計和模擬均使用 TSMC 0.18μm CMOS 1P6M製程技術進行驗證。在正反器方面,供應電壓源為1.8V,雙緣脈波觸發正反器時脈為100MHz,而為了使單緣觸發正反器的資料吞吐量與雙緣觸發相同 其工作頻率設定為為200MHz。另外,在量測平均功率性能方面,輸入資料採用目前文獻經常使用的五種測試樣本,分別對應的資料切換機率為0至100%。接著,在雙模預除器部分,操作電壓為0.6V至0.9V,工作頻率從500MHz至2900MHz。除了2個電路整體的表現皆比先前文獻所提出的電路還要更為優良之外,所有模擬數據皆通過製程變異測試考量(5-Corner,工作溫度:0至100度C),當電路工作於不同的製程變異條件下,皆能提供正確的電路功能。

In this thesis, we proposed two novel circuit designs. The first circuit is a double-edge-triggered fip-flop. A double-edge pulse generator using pass transistor logic (PTL) is derived first. Both threshold voltage loss and poor driving capability problems common in PTL design are successfully resolved while the circuit simplicity is kept. The proposed dual-edge pulse generator, using the signal generated by an internal node, plus the employment of an additional nMOS transistor, overcomes the shortcomings of the original design. The resultant dual-edge-triggered FF design consists of an XOR logic based pulse generator and a level sensitive latch. Circuits used in performance comparison include ep-SFF, ep-DSFF, XNOR-PFF, and the proposed design. Simulation results show that, the proposed design outperform the runner up design by 12.5% in terms of delay time and by 15% in terms of average power consumption.
The second circuit is a novel divide-by-2/3 counter for low voltage and low power applicatioins. Conventional approaches of the 2/3 counter design are to embed additional logic function to the D flip-flop design to speed up the operations. In this thesis, a novel extended true single-phase clock flip-flop based low power divide-by 2/3 counter using only 13 transistors is presented. By using PTL circuit technique, the proposed design successfully reduces the total transistor-count and thus achieves better performances in various aspects. Simulation results indicate that, when compared with previous designs, as much as 12.2% savings in power and 23.4% in power-delay-product can be achieved.
Both circuits were designed and simulated by using TSMC 0.18μm CMOS 1P6M process technology. The simulation conditions for the FF design are as follow: 1.8V supply voltage, 100MHz and 200MHz clock frequencies for the dual-edge- triggered and single-edge-triggered FF designs, respectively. The discrepancy in clock frequency setting is to ensure both types of design encounter the same data throughput. In average power consumption measurements, 5 commonly recognized test patterns featuring a switching probability variation ranging from 0 to 100% were adopted. The simulation conditions for the dual-modulus prescaler design include a sweep in supply voltage from 0.6V to 0.9V, and a operating frequency scan from 500MHz to 2900MHz. Besides the performance advantages over the existing designs, both of the proposed designs were also verified under the various simulation conditions, i.e., (5-Corner, operating temperature: 0 to 100 degrees C) and were proved to function properly in the face of process variations.
URI: http://hdl.handle.net/11455/8978
其他識別: U0005-2708201004245300
Appears in Collections:電機工程學系所

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