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Design and Implementation of Channel Encoding/Decoding System Integration
|關鍵字:||Channel coding;通道編解碼;gaussian noise generator;LDPC;scrambler;高斯雜訊產生器;低密度同位元查核碼||出版社:||電機工程學系所||引用:|| IEEE 802.11a, IEEE standard for information technology Telecommunication and information exchange between systems local and metropolitan area networks Specific requirements. Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHz Band, 1999.  IEEE 802.11g, IEEE standard for information technology Telecommunication and information exchange between systems local and metropolitan area networks Specific requirements. Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Further Higher Data Rate Extension in the 2.4 GHz Band, 2003.  IEEE P802.11n, Draft standard for information technology Telecommunication and information exchange between systems local and metropolitan area networks Specific requirements. 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IEEE 802.15.3c, IEEE standard for information technology Telecommunication and information exchange between systems local and metropolitan area networks Specific requirements. Part 15.3: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs), 2009.||摘要:||
本論文提出通道編解碼系統整合設計與實作，包含幾個主要部份：首先提出Scrambler/Descrambler演算法，其演算法可適用於任意三項多項式，並以最少暫存器數量及最短critical path為考量，其critical path為一個暫存器與一個XOR閘，實作以差動電路合併XOR邏輯閘與暫存器來減少面積與提高速度，並以全客製化佈局之TSMC 0.18μm CMOS製程下線，主電路面積與文獻相較可減少50%，量測結果顯示電路可操作在1.6GHz相當於25.6Gbps，其消耗功率為17.33mW，成果發表於2010 ISCAS 。
其次本論文提出高斯雜訊產生器、LLR解調變電路、LDPC解碼器之整合設計，目的在於改善LDPC設計時的模擬速度，當BER (Bit Error Rate)被要求驗證到10-7以下時，模擬時間將不符效益，以硬體取代軟體是有效加速模擬的方法。以結合Box-Muller algorithm與Wallace method兩種演算法來實現高斯雜訊產生器電路，並通過chi-square goodness-of-fit測試。
LLR解調變電路使用分段線性近似法，在未知雜訊變異數之高斯通道下依據LDPC解碼器來模擬density evolution，搭配數值量化結果來設計。LDPC解碼器為WPAN (Wireless Personal Area Network)之不規則矩陣，電路使用全平行架構設計，並以Limited Layered Min Sum Algorithm來降低運算複雜度，配合shift register-mapping電路繞線技巧減少多工器使用降低面積。最後系統以Xilinx Vertex-4 FPGA將上述電路進行整合，驗證結果顯示能大幅降低模擬時間。
In this thesis, design and implementation of channel encoding/decoding system integration is presented. Firstly, a scrambler/descrambler algorithm is proposed, which can be applied to any scrambler polynomials with three terms for the minimum number of registers and the shortest critical path. The critical paths only have one register and one XOR gate, which can be merged into a differential circuit for implementation to reduce chip area and enhance speed. The design was implemented by full-custom design flow using TSMC 0.18 μm CMOS process. The core-circuit area can be reduced by more than 50% in comparison with literatures. The measurement results reveal that the power dissipation, including that of the clock buffers, is only 17.33mW at 1.6GHz with 16 parallel outputs, which is equivalent to 25.6Gbps. These results were published in 2010 ISCAS.
Secondly, integration of Gaussian noise generator, LLR demodulator, LDPC decoder was performed. The goal is to improve the simulation speed of LDPC decoder. When the bit error rate lower than 10-7 is required for evaluation, the cost of simulation time becomes unfeasible. Using hardware instead of software is an efficient way to increase the speed. Therefore, the Box-Muller algorithm and Wallace method were applied to implement the Gaussian noise generator, which passes chi-square goodness-of-fit test.
For the LLR demodulator, the piecewise linear approximation algorithm over Gaussian channels with unknown noise variance was designed based on the density evolution simulation of LDPC decoder and the quantization of LLR. The circuit of WPAN irregular LDPC with full-parallel architecture was also implemented using limited LMSA to reduce complexity; meanwhile, the special shift register-mapping technique routing skills help decrease the usage of multiplexers. Finally, the system was integrated using Xilinx Vertex-4 FPGA. The verification results reveal that the system reduces the simulation time significantly.
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