Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/8998
標題: 運用場可程式化邏輯閘陣列研討低密度同位元查核碼解碼器之錯誤基數
Study of Error Floor of LDPC Decoders Using FPGA
作者: 黃俊哲
Huang, Jun-Zhe
關鍵字: 低密度同位元查核碼;LDPC;錯誤基數;場可程式化邏輯閘陣列;Error Floor;FPGA
出版社: 電機工程學系所
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Kschischang, “Power Reduction Techniques for LDPC Decoders,” IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1835-1845, Aug. 2008. [17] X. Y. Shih, C. Z. Zhan, and A. Y. Wu, “A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications,” IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 301-304, Nov. 2008. [18] K.Zhang, X. Huang, Z. Wang, “High-Throughput layered decoder implementation for Quasi-Cyclic LDPC codes,”IEEE JSAC, vol. 27, no. 6, Aug. 2009. [19] Bo Xiang, Rui Shen, An Pan, Dan Bao, and Xiaoyang Zeng, “An Area-Efficient and Low-Power Multirate decoder for Quasi-Cyclic Low-Density Parity-Check Codes”, vol. 18, no. 10, Oct.2010. [20] A. Dur, “Avoiding decoder malfunction in the Peterson-Gorenstein-Zierler decoder,” IEEE Trans. Information Theory, vol. 39, pp. 640-643, March 1993. [21] M. Srinvasan, D. V. Sarwate, “Malfunction in the Peterson-Gorenstein-Zierler decoder,” IEEE Trans. Information Theory, vol. 40, pp. 1649-1653, Sep. 1994. [22] H. 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Ye, “VLSI design and implementation of high-speed RS(204,188) decoder,’’ IEEE 2002 International Conference Communications, Circuits and Systems and West Sino Expositions, vol. 1, pp. 82- 86 , July 2002. [28] H.Lee, ’’High speed VLSI architecture for Parallel Reed-Solomon Decoder’’, IEEE Trans.VLSI Integr. Syst., vol. 11, no. 2, pp. 288-294, Apr.2003 [29] Sung-Woo, S.-S. Choi and H. Lee, “RS decoder architecture for UWB’’, International Conference Advanced Communication Technology ICACT., vol.1, pp.805-808, Feb. 2006. [30] T. K. Truong, J. H. Jeng and I. S. Reed, “Fast algorithm for computing the roots of error locator polynomials up to degree 11 in Reed-Solomon decoder,” IEEE Trans. On Communications, vol. 49, no. 5, pp. 779-783, May 1999.
摘要: 
本論文使用Xilinx Virtex4 FPGA實現及驗證所提出之低密度同位元查核碼解碼器電路,使用矩陣大小為512×1024,行權重及列權重分別為3與6之規則建構查核矩陣,在硬體架構上分成五個單元,分別為:變數點單元、查核點單元、重排單元、控制單元與三個訊息記憶體單元。查核點單元以Min-Sum演算法來做為硬體設計原則。
硬體的架構主要使用部份平行式來降低硬體複雜度,並且利用切割矩陣方式使其邏輯閘數減少,為了使硬體有效的使用,我們在這裡利用雙路徑的架構使查核點和變數點在運算完後,可以運算另一組codeword,以等待變數點和查核點更新過後的值,如此可讓傳輸速度提升至原本設計的兩倍。再利用MATLAB和FPGA之間的整合驗證,將設計的硬體電路效能實現出來,並且比較使用軟體所執行出來的結果以及比較各種不同位元數的硬體使用情形,Cell-based所設計為4 bits LDPC架構,經0.18μm製程下線在1.8V量測最高頻率為55MHz;功率消耗在1.62V 下,40MHz所量測結果為114.52mW。
最後驗證使用Reed-Solomon code將LDPC的硬體效能提高,並且避免了LDPC提早出現的Error Floor,有效的降低錯誤值。

In this thesis, Xilinx Virtex4 FPGA was used to implement and verify the proposed LDPC decoder circuit. The (512,1024) check matrix is a regular matrix in which the column weight and the row weight are 3 and 6, respectively. It is composed of five units including a variable node unit (VNU), a check node unit (CNU), a permutation unit (PU), a control unit (CU), and three message memory units (MU). The min-sum algorithm was applied in the CNU.
The proposed partial parallel architecture based on a partition shift matrix to reduce logic gates was utilized. In order to make use of hardware more efficiently, the proposed decoder adopts a dual-path architecture. During calculating the check nodes or variable nodes, the waiting time can be used to compute the variable nodes or the check nodes of another codeword. By doing so, the throughput can be doubled. The proposed hardware performance was verified by co-simulation of MATLAB and FPGA. The comparison of different hardware architechures was also performed. The measurement results of cell-based LDPC architecture with 4 bits using TSMC 0.18 μm CMOS process reveal that the frequency can be 55MHz at VDD=1.8V and the power consumption is 114.52mW with 40MHz at VDD=1.62V.
Finally, the decoding capability of the proposed LDPC decoder can be enhanced by including the Reed-Solomon decoding scheme. It can avoid the error floor phenomenon that occurs in the fixed-point LDPC decoder.
URI: http://hdl.handle.net/11455/8998
其他識別: U0005-2901201112512400
Appears in Collections:電機工程學系所

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