Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9002
標題: 運用三角波轉正弦波轉換技術實現無記憶體式直接數位頻率合成器
ROM-Less Direct Digital Frequency Synthesizers Using a Triangle-to-Sine Convertion Technique
作者: 朱壹麟
Jhu, Yi-Lin
關鍵字: 無記憶體;ROM-Less;數位頻率合成器;DDS
出版社: 電機工程學系所
引用: [1]IEEE Std 802.11aTM-2003, “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer in the 5GHz Band.” [2]IEEE Std 802.11b-1999, “Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer Extension in the 2.4GHz Band.” [3]IEEE Std 802.11gTM-2003, “Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Further Higher Data Rate Extension in the 2.4GHz Band.” [4]J. Tierney, C.M. Rader ,and B. Gold, “ A Digital Frequency Synthesizer, ”IEEE Transcations. on Audio and Electroacoustics., Vol. AU-19 , NO.1, pp.48-57, Mar .1971 [5]P.O’Leary and F.Maloberti, “ A Direct-Digital Synthesizer With Improved Spectral Performance, ” IEEE Trans.Commum, Vol.39, NO.7, pp.1,046-1, 048, July 1991. [6]V.F Kroupa, V. Cizek, J. Stursa, and H. Svandova, “ Spurious Signals In Direct Digital Frequency Synthesizers Due To The Phase Truncation, ” IEEE Trans. Ultrason.,Ferroelect. Freq. Contr., Vol.47, NO.5, pp.1,166-1,172, Sept 2000. [7] F. Curticapean and J.Niittylahti, “Exact Analysis of Spurious Signals In Direct Digital Frequency Synthesizers Due to the Phase Truncation , ” Electron Lett., Vol.39, NO.6, pp.499-501, Mar 2003. [8]X. Yu, F. F. Dai, J. D. Irwin, R. C. Jaeger, “A 9-bit quadrature direct digital synthesizer implemented in 0.18-μm SiGe BiCMOS Technology,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 5, pp.1257-1266, May 2008. [9]X. Yu, F. F. Dai, J. D. Irwin, R. C. Jaeger, “A 12 GHz 1.9 W direct digital synthesizer MMIC implemented in 0.18-μm SiGe BiCMOS Technology,” IEEE J. Solid-State Circuits, vol.43, no. 6, pp.1384-1393, June 2008. [10]Xueyang Geng, Fa Foster Dai, J.David Irwin and Richard C.Faeger “24-bit 5.0GHZ Direct Digital Synthesizer RFIC with Direct Digital Modulations in 0.13 μm SiGe BiCMOS Technolory,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 5, MAY 2010. [11]E.S Vinck, “Analysis and Synthesis of Translinear Intergrated Circuits,” Elsevier Science Publisher B.V, 1988. [12]John W.Fattaruso,and Robert G. Meyer “Triangle-to-Sine Wave Conversion With MOS Technology,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, sc-20, NO. 2, April 1985. [13]B. Razavi, Design of Analog CMOS Integrated Circuits, Ch. 4, McGraw-Hill, 2001. [14]D.A John and K. Martin, “Analog Integrated Circuit Design, ” John Wiley & Sons Inc.,1997 [15]R.van de Plassche, “Intergrated Analog-to-Digital and Digital-to Analog Converters, ”Kluwer Academic Publishers,1994. [16]Walt Kester, James Bryant, “Sample Data System , ” Analog Devices Inc. [17]Chi-H Lin, K.Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,"IEEE Journal of Solid-State Circuits,vol.33, pp.1948-1958, Dec. 1998. [18]Y. Cong and R. Geiger, “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoder DAC Arrays, ” IEEE Transcation on Circuit and Symtems II, vol.47,NO 7, pp.585-595, July. 2000 [19]T. Miki Y. Nakamura et al. , “A 80-MHz 8-b CMOS D/A Converter, ” IEEE Journal of Solid-State Circuits,vol.21, pp.983-988,Dec 1986. [20]M. M. Mano , “Digital Design 3rd edition, ”Prentice Hall, 2002 [21]P.C.Hills “MOS Triangle-to-Sine Wave Convertor Based on Subthreshold Operation ,”Electronics Letters 8th November 1990 Vol.26 No.23 [22]Robert G. Meyer, Willy M.C. Sansen ,Sik Lui,and Stefan Peeters “The Differential Pair as a Triangle-Sine Wave Converter,”IEEE Journal of Solid-State Circuits, June 1976. [23]B. Razavi, “Priciples of Data Conversion System Design,” IEEE Press, 1995. [24]S. Mortezapour and Edward K. F. Lee, “Design of Low –Power ROM-Less Direct Digital Frequency Synthesizer Using Nonlinear Digital-to-Analog Converter,”IEEE J. Solid-State Circuits, vol. 34, no. 10, Oct, 1999. [25]D. D. Caro, N. Petra, and A. G. M. Strollo, “A 380MHZ direct digital synthesizer/mixer with hybrid CORDIC architecture in 0.25μm CMOS” IEEE J. Solid-State Circuits, vol. 42, no.1, Jan. 2007. [26]A. G. M. Strollo, D. DeCaro, and N. Petra, “A 630MHz, 76mW direct digital frequency synthesizer using enhanced ROM compression technique” IEEE J. Solid-State Circuits, vol.42, no.2, Feb. 2007. [27]A. Ashrafi and R. Adhami, “Theoretical upperbound of the spurious-free dynamic range in direct digital frequency synthesizers realized by polynomial interpolation methods,” IEEE Trans. Circuits Syst. I, vol.54, no.10, Oct. 2007. [28]S. Thuries, E. Tournier, A. Cathelin, S. Godet, J. Graffeuil, “A 6-GHz low-power BiCMOS SiGe:C 0.25 μm direct digital synthesizer,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 1, pp.46-48, Jan. 2008. [29]Z. Zhou and G. S. L. Rue, “A 12-bit nonlinear DAC for direct digital frequency synthesis,” IEEE Trans. Circuits Syst. I: Regular Papers, vol.55, no.9, pp. 2459-2468, Oct. 2008. [30]Xueyang Geng, Fa Foster Dai, J.David Irwin and Richard C.Faeger”A 5GHz Direct Digiter Synthesizer MMIC with Direct Modulation and Spur Randomization”, 2009 IEEE Radio Frequency Integrated Circuits Symposium [31] Hong Chang Yeoh, Jae-Hun Jung, Yun-Hwan Jung,and Kwang-Hyun Baek ”A 1.3GHz 350mW Hybrid Direct Digital Frequency Synthesizer in 90nm CMOS” ,2009 Symposium on VLSI Circuits Digest of Technical Papers [32] J, Jiang and E, K. Lee, “A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter,” IEEE Custom Integrated Circuits Conference , 2001 [33] Xueyang Geng,student Member,IEEE,Fa Foster Dai,Fellow,IEEE,J.David Irwin,Life Fellow,IEEE,and Richard C.Jaeger,Life Fellow,IEEE”A 11-Bit 8.6GHz Direct Digital Synthesizer MMIC with 10 Bit segmented Sin-Weighted DAC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 2, FEBRUARY 2010 [34] 溫錦炘,無記憶體直接數位頻率合成器之設計與分析,國立中興大學電機工程學系研究所碩士學位論文,2007
摘要: 
頻率合成器大致可分為鎖相迴路及直接數位頻率合成器兩種形式,本論文採用直接數位頻率合成器,包括原理介紹及不同架構的區別,也提出不同於傳統架構的無記憶體式直接數位頻率合成器,並加以改善。我們提出使用三角轉弦波信號的類比電路的作法,採取其無記憶體式直接數位頻率合成器的優點,捨棄了記憶體,並結合了傳統直接數位頻率合成器所採用的線性的數位類比轉換器,比起一般的無記憶體式直接數位頻率合成器,在面積與功率消耗的特性,更具有其優勢,設計上也較採用非線性的數位類比轉換器容易,且整體系統皆為CMOS製程,方便與CMOS數位電路做結合。此外,我們所只用的三角轉弦波信號的類比電路是本篇論文的研究重點之一,因為一切的起源都由三角轉弦波信號的類比電路開始,論文中也詳盡的去研究、分析三角轉弦波信號的類比電路,並朝向高速的設計方式來實現無記憶體式直接數位頻率合成器。


本論文將有三顆晶片做驗證,第一顆晶片實作為一個運用Translinear Loop 實現三角轉弦波信號的類比電路,所使用的製程為0.18um CMOS,消耗功率為56mW,量測結果可達到7bit的解析度,而第二顆晶片,同樣使用0.18um CMOS製程,為一個取樣頻率2GHz之8位元數位類比轉換器,並使用差動對的三角轉弦波信號類比電路實現無記憶體式直接數位頻率合成器,電路面積為0.81mm ×0.64mm,功率消耗為72mW,量測結果可達到7.5bit解析度,操作頻率可達到1.5GHz ,最後一顆晶片使用90nm CMOS製程,為一個模擬結果電路可操作至7.5GHz,SFDR最高可達48dB,電路面積為1.3mm ×0.98mm,功率消耗為182mW之無記憶體式直接數位頻率合成器。

There are two kinds of frequency synthesizers include of the phase lock loop based synthesizer and the direct digital frequency synthesizer (DDFS). In this thesis we adopt the DDFS. We will introduce the theorem and the difference between the different structures on DDFS. A new ROM-less DDFS is proposed it. Which uses the method of Triangle-to-Sine Converter, TSC. In the traditional structure of DDFS ,linear digital to analog converter ,and ROM-less DDFS present good power consumption and small chip-area. Both get advantage from traditional DDFS and ROM-less DDFS ,which we used. And the whole system is fabricated in CMOS process. It is convenient to combine with CMOS digital circuit. Otherwise the Triangle-to-Sine Converter is key point in this paper. In this paper we studied and analyze the TSC. When we design the all structure, we demand not only saving area but also higher speed to work out. Because Triangle-to-Sine Converter is the source of everything.


Thus, there are three chips designed in this paper. The first one is application of Translinear Loop to achieve TSC. The chip is implemented in 0.18 um CMOS, and the power consumption is about 56mW. The measured resolution is up to 7 bit. The second ones is also implemented in 0.18um CMOS technology with 8bit 2GS/S digital to analog converter. We used the differential pair's TSC to achieve ROM-less DDFS, resulting in the die area of 0.81mm ×0.64mm and the power consumption of 72mW. The measured resolution is up to 7.5 bit, while the operation speed is up to 1.5GHz. Using 90nm CMOS processing can operate at 7.5GHz, while maximum SFDR is 48dB, the dia area is 1.3mm ×0.98mm, and the power consumption is 182mW.
URI: http://hdl.handle.net/11455/9002
其他識別: U0005-2911201016385300
Appears in Collections:電機工程學系所

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