Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9015
標題: 應用於智慧型節能屋電力監控系統之電力線傳輸前端電路
Front-End Circuits of Power Line Communication for the Application of Intelligent Electric Power Control Systems in Energy Saving Houses
作者: 黃祥恩
Huang, Hsiang-En
關鍵字: 自動增益控制器;AGC;功率放大器;自我震盪功率放大器;PA;SOPA
出版社: 電機工程學系所
引用: [1]. Miura, N.,Sato, H.,Narita, H.,Takaki, M. ,“Automatic meter-reading system by power line carrier communications,” IEE Proc. Generation, Transmission and Distribution, vol. 137, Issue 1, pp.25 - 31, Jan 1990. [2]. Raymond H. Kelley, Richard Christopher Carpenter, Robert H. Lunney, Maureen Martinez, “Automated meter reading system,” United States Patent, 11 Jul 2000. [3]. Michael B., David L., “POWER LINE COMMUNICATION APPARATUS,”European Patent, 27 Sep 1995. [4]. H.A. Latchman, K. Afkhamie, S. Katar, R.E. Newman, B. Mashburn and L. Yonge, “High speed multimedia home networking over powerline,” National Cable and Telecommunications association (NCTA) National show, April 2005. [5]. L. Scott Humphries, Glenn Rasmussen, Douglas L. Voita, James D. Pritchett,“Home automation system,” United States Patent, 15 Apr 1997. [6]. http://www.pulseworx.com/downloads/upb/UPBDescriptionv1.4.pdf [7]. “Communication Systems 4thED”, Haykin, John Wiley & Sons. [8]. “Advanced electronic communications systems, 4thed.”, Wayne Tomasi. [9]. Y. H. Ma, P. L. So, and E. Gunawan, “Performance analysis of OFDM systems for broadband power line communications under impulsive noise and multipath effects,” IEEE Trans. Power Delivery, vol. 20, no. 2, pp. 674-682, Apr. 2005. [10]. Y-F. Chen, T-D. Chiueh, “Baseband Transceiver Design of a 128-kbps Power- Line Modem for Household Applications”, IEEE Transactions on Power Delivery,vol. 17, No. 2, Apr. 2002. [11]. Biglieri, E. Politecnico di Torino;“Coding and modulation for a horrible channel” HCommunications Magazine, IEEEH, Volume: 41,Issue: 5 On page(s): 92- 98, may 2003. [12]. P. Amirshahi, S. M. Navidpour, and M. Kavehrad,“Performance analysis of uncoded and coded OFDM broadband transmission over low voltage power-line channels with impulsive noise,” IEEE Trans. Power Delivery, vol. 21, pp. 1927-1934, Oct. 2006. [13]. Y.-J. Lin, H. A. Latchmane R. E. Newman, “A comparative performance study of wireless and power line networks., IEEE CommunicationsMagazine, ” vol. 41, no. 4, pp. 54.63, abril de 2003. [14]. Yu-ju Lin , Haniph A. Latchman, Minkyu Lee and Srinivas Katar,“Power line Communication Network Infrastructure For Smart Homes”, IEEE Wireless Communications, Volume 9, Issue 6, Pages:104-111, December, 2002. [15]. Sungsoo Choi ,Won-Tae Lee ,Sungha Yun ,Young-Chul Rhee,;“SoC design and implementation for high reliable narrow-band power-line communications,” ISPLC 2008. IEEE International Symposium on , vol., no., pp.399-403, 2-4 April 2008. [16]. HHagen, M.H,HHeminger, M.H,HMohammed, A.H, “Power line communication for lighting applications using binary phase shift keying (BPSK) with a single DSP controller,” HApplied Power Electronics Conference and Exposition, 2006. APEC ''06., 19-23 March 2006. [17]. N. Pavlidou, A. J. H.Vinck, J. Yazdani, and B. Honary, “Power line communications: State of the art and future trends,” IEEE Commun. Mag.,vol. 41, pp. 34-40, Apr. 2003. [18].ST7540 FSK powerline transceiver design guide for AMR [19].Zhiheng Chen ”A Direct-Conversion CMOS Radio Receiver for High Speed Paging”. [20]. Hung Yan Cheung, King Sau Cheung, Jack Lau “ A low power monolithic AGC with automatic DC offset cancellation for direct conversion CDMA receiver”. [21]. Chih-Wen Lu, Member, IEEE “A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Driver” IEEE Journal of solid-state circuit, vol, 44, no. 2, February. [22]. Walter Aloisi, Giuseppe Di Cataldo, Gianluca, Palumbo “Design guidelines of CMOS class-AB output stages : a tutorial”. [23]. Tim Piessens, Michiel Steyaert “Design and Analysis of High Efficiency Line Drivers for xDSL.” [24]. James H. Taylor “Describing Function”. [25]. Daniel Karssen, Martijn Wisse “Tutorial : Limit cycle analysis”. [26]. Tim Piessens, Michiel S. J. Steyaert. “Behavioral Analysis of Self-Oscillating Class D Line drivers”. IEEE Transactions on Circuits and System : Regular papers. Vol. 52. no. 4, April 2005 [27]. Tim Piessens, Michiel Steyaert “Design Considerations and Experimental Verification of a Self Oscillating Line Driver in .35 um CMOS”. [28]. Tim Piessens, Michiel Steyaert “Oscillating Pulling and Synchronisation Issues in Self-Oscillating Class D Power Amplifiers”. [29]. Brian S. Cherkauer, Eby G. Friedman “A Unified Design Methodology for CMOS Tapered Buffers” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3. no. 1, March 1995. [30]. Srinivasa R. Vemuru, Arthur R. Thorbjornsen “Variable-Taper CMOS Buffer” IEEE Journal of solid-State Circuit, vol. 26, no. 9, September 1991. [31]. Tim Piessens, Michiel Steyaert, “Highly Efficiency xDSL Line Drivers in 0.35-um CMOS Using a Self-Oscillating Power Amplifier” IEEE Journal of Solid-State Circuits. Vol. 38. no. 1, January 2003
摘要: 
本論文在此實現一電力線傳輸前端界面電路,係利用電器之供電電力線作為資料傳輸媒介,提供電力線通道雜訊的抑制與訊號放大之機制,且有效的將110伏大電壓與傳送接收(Tx/Rx)前端電路做隔絕。結合各電器節點所搭配之微處理機 (Micro-processor Unit, MPU)和可程式邏輯閘陣列(Field Programmable Gate Array, FPGA),與中央監控系統做連結,進行控制訊號與節點資料的雙向傳輸。
而電路架構包含了耦合介面電路、自動增益控制器、以及功率放大器。耦合介面電路提供110 V大電壓的隔絕,並結合功率放大器形成主動濾波器,對電力線上之高頻雜訊進行抑制。功率放大器則是使用0.35-um CMOS製程,為一個軌對軌Class-AB之電路架構,利用輸入級之雙重補償差動對放大器,以及輔助轉導放大器,提供了全幅的輸入範圍以及良好的驅動能力。而自動增益控制器所使用製程為0.18-um CMOS。其功能是對電力線傳輸之接收端進行訊號放大的功能,由於傳輸過程中訊號會受到雜訊干擾以及路徑所造成之衰退,造成接收端讀取的困難。透過自動增益放大器可將所接收之大小不一的訊號,放大至同一位準,其增益調整能力可從-51.4dB~64.2 dB。
最後則考慮使用一自我震盪功率放大器之架構,作為電力線前端電路之驅動器。自我震盪功率放大器為Class-D功率放大器之改良,對於傳統的Class-D切換式功率放大器來說容易遇到失真的限制,而由於自我震盪功率放大器的非線性連續時間特性,其具有了罕見的高線性度以及高效率,在此可達到53%之效率,SFDR與THD分別為53.6 dB以及52.8 dB,而所使用之製程為0.35-um CMOS製程。

In the thesis, a front-end interface circuit is proposed, which use power line as data transmission medium. The front-end circuit can provide power line channel noise suppression, signal amplification, and isolating the 110 volts from receiver and transmitter. Combine with the microprocessor, and programmable gate array of the electric equipment to the central monitoring system, as a two-way data transmission link for control signals.
The circuit architecture includes a coupling interface circuit, automatic gain controller, and power amplifier. Interface coupled circuit provide high voltage isolation, combined with power amplifier to form active filters, high frequency noise on power line can be greatly suppressed. Power amplifier is implemented with 0.35- um CMOS for a rail to rail Class-AB architecture, the use of the dual complementary differential amplifiers of input stage, and auxiliary transconductance amplifier, providing a full range of width of the input and good driving capabilities. The automatic gain controller is implemented with 0.18 um CMOS, which amplified the signal from power line at receiver. Because during the transmission process, signal will be interfered by noise and caused decadence by transmission path, so receiver can not read properly. Through automatic gain controller, different signal amplitudes can be amplified to the standard level with its gain turning range from -51.4dB ~ 64.2 dB, while the circuit is implemented with 0.18-um CMOS.
Finally, consider the structure of a self-oscillation power amplifier, for power line driver. Self-oscillation power amplifier is the improved Class-D power amplifier. The conventional Class-D switching power amplifier is vulnerable to distortion constraints. Due to the non-linear continuous time nature of the self-oscillation, it possesses peculiar properties that enable the construction of a highly linear, high efficiency line driver. In the thesis which has efficiency up to 53%, SFDR and THD are 53.6 dB and 52.8 dB respectively. A prototype has been fabricated in a 0.35-um CMOS process to demonstrate the proposed circuit.
URI: http://hdl.handle.net/11455/9015
其他識別: U0005-3011201009511300
Appears in Collections:電機工程學系所

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