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標題: 低功耗逐步近似暫存式類比數位轉換器設計
Low Power Successive Approximation Register Analog to Digital Converter Design
作者: 葉昆明
Kun-Ming Yeh
關鍵字: ADC;類比數位轉換器
引用: [1] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995. [2] W. A. Kester, Data Conversion Handbook, Newnes, 2005. [3] IEEE Standard for Digitizing Waveform Recorders. IEEE, 1994. [4] R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, John Wiley & Sons, 2011. [5] F. Maloberti, Data Converters, Springer, 2007. [6] M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations, Springer, 2006. [7] B. Razavi, Design of Integrated Circuits for Optical Communications, John Wiley & Sons, 2012. [8] M. J. M. Pelgrom, Analog-to-Digital Conversion, Springer, 2012. [9] Y. Chen, S. Tsukamoto, and T. Kuroda, 'A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS,' in Proc. IEEE Asian Solid-State Circuits Conference, Nov. 2009, pp. 145–148. . [10] L. Sumunen, M. Wulturi, and K. Hulonen, 'A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters,' in Proc. The 7th IEEE International Conference on Electronics, Circuits and Systems, Dec. 2000, vol. 1, pp. 32–35. [11] L. Sumanen, M. Waltar, V. Hakkarainen, and K. Halonen, 'CMOS dynamic comparators for pipeline A/D converters,' in Proc. IEEE International Symposium on Circuits and Systems, May 2002, vol. 5, pp. V–157–V–160. [12] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, 'A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,' IEICE Trans. on Electronics, vol. E76–C, no. 5, pp. 863–867, May 1993. [13] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, 'Yield and speed optimization of a latch-type voltage sense amplifier,' IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004. [14] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2002. [15] T. O. Anderson,'Optimum control logic for successive approximation analog-to-digital converters,'Computer Design, vol. 11, no. 7, pp. 81–86, 1972. [16] M. D. Scott, B. E. Boser, and K. S. J. Pister, 'An ultralow-energy ADC for smart dust,' IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1123–1129, Jul. 2003. [17] A. M. Abo and P. R. Gray, 'A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,' IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999. [18] F. Kuttner, 'A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS,' in Proc. IEEE International Solid-State Circuits Conference, Feb. 2002, vol. 1, pp. 176–177. [19] M.-L. Fan, 'Successive Approximation Analog-to-Digital Converter for Low Power System Application, ' Department of Electrical Engineering, NCKU Master Thesis, Jul. 2012.
This thesis presents the design of an analog to digital converter (ADC) with low power consumption, which is suitable for portable electronic applications powered by batteries such as mobile phone, digital camera, PDA, etc. To reduce power consumption of conversion, a successive approximation registers (SAR) analog to digital converter can be used. An eight-bit SAR ADC utilized binary search charge distribution digital to analog converter to increase the circuit linearity. To obtain both high speed and low power, latch only comparator and bootstrapped switch are used.
  The SAR ADC is designed and simulated by HSPICE with TSMC 0.18μm 1P6M 1.8V/3.3V Mixed Signal CMOS technology. The supply voltage of the 8-bit SAR ADC is 1.8V and the sampling rate is 5KHz. Its power consumption is 1100μW.

  此類比數位轉換器是使用台灣積體電路製造股份有限公司所提供的0.18μm 1P6M 1.8V/3.3V Mixed Signal CMOS製程技術來設計與製造,並利用Hspice進行電路模擬。在供應電壓1.8V下,此八位元類比數位轉換器的取樣頻率為5KHz,功率消耗為1100μW。
其他識別: U0005-2310201315135900
Rights: 同意授權瀏覽/列印電子全文服務,2016-12-30起公開。
Appears in Collections:電機工程學系所

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