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標題: p-i-n型低溫複晶矽薄膜電晶體在直流電壓應力下退化機制之研究
Study on the Degradation Mechanism of p-i-n type LTPS TFTs under DC Bias Stress
作者: 曹煒豐
Wei-Fong Cao
關鍵字: hot carrier effect;tunnel poly-si TFTs;熱載子效應;穿隧型複晶矽薄膜電晶體
引用: [1] Satoshi INOUE, Mutsumi KIMURA and Tatsuya SHIMODA, 'Analysis and Classification of Degradation Phenomena in Polycrystalline-Silicon Thin Film Transistors Fabricated by a Low-Temperature Process Using Emission Light Microscopy' Jpn. J. Appl. Phys. Vol. 42, No. 3, pp. 1168–1172,2003. [2] Mark D. Jacunski, Michael Hack, and Benjam´ın I˜n´ıguez, 'A Short-Channel DC SPICE Model for Polysilicon Thin-Film Transistors Including Temperature Effects', IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 6,pp.1146-1158,1999. [3] Ya-Hsiang Tai, Shih Che Huang,z and Hao Lin Chiu, 'Degradation of Capacitance-Voltage Characteristics Induced by Self-Heating Effect in Poly-Si TFTs', Electrochemical and Solid-State Letters,vol, 9,pp. G208-G210,2006. [4] Chih-Yang Chen, Jam-Wem Lee, Shen-De Wang, Ming-Shan Shieh, Po-Hao Lee, Wei-Cheng Chen, Hsiao-Yi Lin, 'Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors', IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 12,pp.2993-3000,2006. [5] A. Khamesra, R. La1 , J. Vasi, A. Kurriar K. P.* and J. K. 0. Sin*,'Device Degradation of n-channel Poly-Si TFT's due to High-Field, Hot-Carrier and Radiation Stressing', Proceedings of 8' IPFA 2001, Singapore,2001. [6] Sung-Hwan Choi, Sun-Jae Kim, Yeon-Gon Mo1, Hye-Dong Kim1, and Min-Koo Han, 'Reliability in Short-Channel p-Type Polycrystalline Silicon Thin-Film Transistor under High Gate and Drain Bias Stress' Japanese Journal of Applied Physics,vol.49,no3,2010. [7] Nikolaos A. Hastas, Charalabos A. Dimitriadis, Jean Brini, and George Kamarinos, 'Hot-Carrier-Induced Degradation in Short p-Channel Nonhydrogenated Polysilicon Thin-Film Transistors' IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 9,pp.1152-1157,2002. [8] Kook Chul Moon, Jae-Hoon Lee, and Min-Koo Han, 'The Study of Hot-Carrier Stress on Poly-Si TFT Employing C–V Measurement' IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 4,pp.512-517,2005. [9] Ya-Hsiang Tai, Shih-Che Huang, and Po-Ting Chen 'Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region' IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 3,pp231-233,2009. [10] Ya-Hsiang Tai, Shih-Che Huang, Chun-Wen Lin, and Hao Lin Chiu 'Degradation of the Capacitance-Voltage Behaviors of the LTPS TFTs under DC Stress', JOURNAL OF THE ELECTROCHEMICAL SOCIETY, Vol. 154, No. 7, pp. H611-H618, 2007 [11] Han-Wen Liu , Si-Ming Chiou, and Fang-Hsing Wang, 'Turn-Around Phenomenon in the Degradation Trend of n-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors under DC Bias Stress', Japanese Journal of Applied Physics,vol. 49,pp.074103,2010.
Low-temperature Poly-Si thin film transistor(LPTS) TFTs than the amorphous silicon TFTs, a higher carrier mobility and the opening ratio.LTPS TFTs were widely used in the new generation of displays, especially in recent years, smart phones are using, so elements Reliability analysis is very important. This paper was to explore the traditional p channel or n channel is not the same p-i-n LTPS TFTs. Such p-i-n LTPS TFTs, by giving a different gate voltage, so that the channel region to produce hole layer, to form a similar n-type or p-type semiconductor layer, and then use a different drain voltage, and drain or source at one end to produce extremely depletion region, so the reliability of such elements may take advantage of the operating mode of the second polar body to explore.
First, we discuss the nature of the electrical characteristics of pin low temperature polysilicon thin film transistor of the n + p + side end or given different negative voltage, the gate give -20 V ~ 20 V, you will find the end to give greater and greater n + negative voltage, can lead to leakage current element sudden rise, while the p + side to give greater negative voltage, and the traditional p-type element to convert a similar curve, so the theory from the esp analyze output characteristics of Id-Vd figures and capacitor to explore the graph voltage pin low polycrystalline silicon thin film transistor is turned on and off mechanism.
Finally, we explore the p-i-n LTPS TFTs reliability were given four different sets of voltage stress conditions, such as (1) Vg = -5 V, -10 V, -15V, Vn = 15 V, (2) Vg = 5 V, 10 V, 15V, Vn = 15 V, (3) Vg = -5 V, -10 V, -15V, Vp = -15V, (4) Vg = 5 V, 10 V, 15V, Vp = -15V, to study the electron or hole with the n-channel region + or p + terminal end reverse bias due to the depletion region is formed, resulting in a large electric field, causing transistor device degradation, degradation occurs in the region which end, it will affect element conduction current, maximum transduction and threshold voltage. Finally, we propose a mechanism element of a recession, then by sampling current, capacitance - voltage measurement, forward reverse - measuring the amount of current and voltage to be verified.

首先,我們探討p-i-n低溫複晶矽薄膜電晶體的本質電的特性在n+端或p+端給予不同的負電壓,閘極給予-20 V~20 V時,會發現給予n+端愈來愈大的負電壓,會導致元件的漏電流急遽上升,而在p+端給予愈大的負電壓時,與傳統的p型元件轉換特性曲線類似,故本論由尤分析Id-Vd的輸出特性圖和電容對電壓的曲線圖來探討p-i-n低溫複晶矽薄膜電晶體導通和關閉機制。
最後,我們探討p-i-n 低溫複晶矽薄膜電晶體的可靠度分別給予四組不同的電壓應力條件如(1) Vg=-5 V、-10 V 、-15V ,Vn=15 V ,(2) Vg=5 V、10 V 、15V ,Vn=15 V ,(3) Vg=-5 V、-10 V 、-15V ,Vp=-15V,(4) Vg=5 V、10 V 、15V ,Vp=-15V,去研究通道區域內的電子或電洞與n+端或p+端因逆向偏壓形成的空乏區,產生了大電場,導致電晶體元件退化,退化的區域發生在哪一端,會影響到元件的導通電流、最大轉導和臨界電壓。最後,我們提出了元件的衰退機制,再藉由取樣電流、電容-電壓量測、順向反向-電流電壓量測來加以驗證。
其他識別: U0005-2608201519544500
Rights: 同意授權瀏覽/列印電子全文服務,2018-08-27起公開。
Appears in Collections:電機工程學系所

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