Please use this identifier to cite or link to this item:
標題: 完全相容於CMOS製程之嵌入式MTP記憶體與切換電容式降壓器電路設計
The Fully CMOS Compatible Multiple-Time-Programmable Memory Circuits and Switched-Capacitor DC-DC Converter Design
作者: 黃智揚
Huang, ChihYang
關鍵字: 非揮發性記憶體;non-volatile memory;多次性寫入;高電壓驅動電路;高電壓隔離電路;切換電容式降壓器;multiple-time-programmable;high voltage driver;high voltage isolation;switched-capacitor DC-DC converter
出版社: 電機工程學系所
引用: [1] Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded nonvolatile memory applications,” Symp. VLSI Tech. Dig., 2003, pp.93-94. [2] Hsiu-Fen Chou, et al., “Comprehensive study on a novel bidirectional tunneling program/erase NOR-type (BiNOR) 3-D flash memory cell,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1386-1393, Jul. 2001. [3] Chang Sean, et al., “New buried bit-line NAND (Bi-NAND) Flash memory for data storage,” Symp. VLSI Tech. Dig., pp. 95-96, 2003. [4] 賴彌元, “Circuits and Systems Design for Multi-level Identifying Embedded EEPROM,” 2008年碩士論文,中興大學. [5] 林映助, “Circuits and Systems Design for Embedded EEPROM,” 2007年碩士論文,中興大學. [6] 鍾秋嬌, “Bi-level and Multi-level Sensing/Verifying Related Circuit Design for Non-Volatile Memories,” 2007年博士論文,中興大學. [7] 陳志興, “Design of Low-Power Embedded Nonvolatile Memory System and Control Signal Generator,” 2006年碩士論文,中興大學. [8] Kung-Hong Lee, Shih-Chen Wang and Ya-Chin King, “Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory,” IEEE International Workshop on Memory Technology, Design, and Testing, 2005, pp.3-8. [9] Kung-Hong Lee, Shih-Chen Wang and Ya-Chin King, “Self-convergent scheme for logic-process-based multilevel/analog memory,” IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2676-2681, Dec. 2005. [10] 李昆鴻, “Study of High-Qensity Embedded Single-Polysilicon Nonvolatile Memory,” 2005年博士論文,清華大學. [11] Ming-Dou Ker and Yan-Liang Lin, ”2xVDD-Tolerant I/O Buffer with 1xVDD CMOS devices,” IEEE Custom Integrated Circuits Conference, 2009, p.539-542. [12] A. J. Annema, G.J.G.M. Geelen and P.C. de Jong, “5.5-V I/O in a 2.5-V 0.25-μm CMOS technology”, IEEE J. Solid-State Circuits, vol. 36, pp. 528-538, March 2001. [13] V. Prodanov and V. Boccuzzi, “7-V tristate-capable output buffer implemented in standard 2.5-V CMOS process,” IEEE Conference on Custom Integrated Circuits, 2001, pp. 497-500. [14] B. Serneels, M. Steyaert and W. Dehaene, “A 5.5 V SOPA line driver in a standard 1.2 V 0.13 mm CMOS technology,” Proceedings of the European Solid-State Circuits Conference, 2005, pp. 303-306. [15] Chih Yang Huang and Hongchin Lin, “High-Voltage-Tolerant Level Converter for Embedded Complementary Metal-Oxide-Semiconductor Nonvolatile Memories,” Japanese Journal of Applied Physics, vol. 51, pp.02BE08-1~02BE08-4, Feb. 2012 [16] N. Shibata, M. Watanabe and H. Okiyama, “A high-speed low-power multi-VDD CMOS/SIMOX SRAM with LV-TTL level input/output pins-write/read assist techniques for 1-V operated memory cells,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1856-1869, Sep. 2010. [17] Neil H. E. Weste and David Harris, CMOS VLSI Design : A Circuits and Systems Perspective. Addison Wesley, 2004. [18] Chiu-Chiao Chung, Hongchin Lin and Yen-Tai Lin, “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp.515-522, Feb.2005. [19] Chiu-Chiao Chung, Hongchin Lin and Yen-Tai Lin, “A multilevel read and verifying scheme for Bi-NAND flash memory,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1180-1188, May 2007. [20] Anh-Tuan Do, et al., “Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM,” IEEE Trans. Very Large Scale Integrate Systems, vol. 19, no. 2, pp. 196-204, Feb. 2011. [21] Steevan Rodrigues and M. S. Bhat, “Impact of Process Variation Induced Transistor Mismatch on Sense Amplifier Performance,” International Conference on Advanced Computing and Communications, 2006, pp.497-502. [22] S.-H. Woo, et al., “Offset voltage estimation model for latch-type sense amplifiers,” IET Circuits Devices Systems, 2010, pp. 503-513. [23] Mudit Bhargava, et al., “Low-Overhead, Digital Offset Compensated, SRAM Sense Amplifiers,” IEEE Custom Integrated Circuits Conference, 2009, pp. 705-708. [24] Taejoong Song, et al., “A robust latch-type sense amplifier using adaptive latch resistance,” IEEE International Conference on IC Design and Technology, 2010, pp. 182-185. [25] D. Schinkel, et al., “A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time,” IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 314-315. [26] Meng-Fan Chang, et al., “An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory,” IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp. 206-208. [27] Chia-Tsung Cheng, et al., “A high-speed current mode sense amplifier for Spin-Torque Transfer Magnetic Random Access Memory,” IEEE International Midwest Symposium on Circuits and Systems, 2011, pp.181-184. [28] Oghenekarho Okobiah, et al., “Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier,” International Conference on VLSI Design, 2012, pp.310-315. [29] Edward N. Y. Ho, et al., ”Design optimization of an output capacitor-less low dropout regulator with compensation capcitance reduction and slew-rate enhancement technique,” IEEE International Symposium on Circuits and Systems, 2011, p.53-56. [30] Pradeep Chhawchharia, et al., ”On the performance improvement for design optimization of buck convertors,” International Conference on Power Electronics and Drive Systems, 1997, p.570-575. [31] Biswajit Maity, et al., ”Hybrid control voltage regulator for switched capacitor based embedded DC-DC buck converter,” International Conference on Electronics Computer Technology, 2011, p.219-222. [32] 吳健誠, “A Pure CMOS Voltage Reference Circuit with Temperature Drift Calibration and an Improved Capacitor-Free Low Dropout Regulator,” 2010年碩士論文,中興大學. [33] Ling Su, et al., “Monolithic reconfigurable SC power converter with adaptive gain control and on-chip capacitor sizing,” IEEE Energy Conversion Congress and Exposition, 2010, pp. 2713-2717. [34] Omar Al-Terkawi Hasib, et al., “A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices,” IEEE Transactions on Biomedical Circuits and Systems, vol. 5, no. 3, pp. 292-301, June 2011. [35] Ling Su, et al., “Design and Analysis of Monolithic Step-Down SC Power Converter With Subthreshold DPWM Control for Self-Powered Wireless Sensors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 1, pp. 280-290, Jan. 2010. [36] Biswajit Maity, et al., “A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications,” IEEE Transactions on Very Large Scale Integration, vol. PP, no. 99, pp. 1-5, Early Access Articles. [37] Ka Nang Leung, et al., “Analysis of multistage amplifier frequency compensation,” IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol. 48, no. 9, pp. 1041-1056, Sep. 2001. [38] G. Palmisano, et al., “An optimized compensation strategy for two-stage CMOS OPAMPs,” IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications, vol. 42, no. 3, pp. 178-182, Mar. 1995. [39] BHUPENDRA K. AHUJA, “An improved frequency compensation technique for CMOS operational amplifiers,” IEEE J. Solid-State Circuits, vol. 18, no. 6, pp. 629-633, Dec. 1983. [40] P. K. Chan, et al., “Gain-enhanced feedforward path compensation technique for pole-zero cancellation at heavy capacitive loads,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no.12, pp. 933-941, Dec. 2003. [41] Akira Yamazaki, et al., “A Frequency Compensation Technique for Variable Output Low Dropout Regulators,” IEEE Asia Pacific Conference on Circuits and Systems, 2006, pp. 1595-1598. [42] Nabil M. Sinoussi, et al., “A novel technique to enhance the stability and the supply rejection of a Miller compensated LDO,” International Design and Test Workshop, 2009, pp. 1-5. [43] Annajirao Garimella, et al., “Frequency compensation techniques for op-amps and LDOs: A tutorial overview,” IEEE International Midwest Symposium on Circuits and Systems, 2011, pp. 1-4. [44] Ruud G. H. Eschauzier, et al., “A 100-MHz 100-dB operational amplifier with multipath nested-Miller compensation,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992. [45] Ka Nang Leung, et al., “Nested Miller compensation in low power CMOS design,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 4, pp. 388-394, Apr. 2001. [46] Gaetano Palumbo, et al., “Design methodology and advances in nested-Miller compensation,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, No. 7, Jul 2002, pp. 893-903. [47] Xiaohua Fan, et al., “Single Miller capacitor frequency compensation technique for low-power multistage amplifiers,” IEEE J. Solid State Circuits, vol. 40, no. 3, pp. 584-592,March 2005. [48] Maneesh Menon, et al., “Low Power Cascaded Three Stage Amplifier with Multipath Nested Miller Compensation,” International Conference on Recent Trends in Information, Telecommunication and Computing, 2010, pp. 9-12. [49] Pawel Fiedorow, et al., “Design and implementation of general purpose opamp using multipath frequency compensation,” IEEE International New Circuits and Systems Conference, 2011, pp. 446-449. [50] Wei Chen, et al., “Switched-capacitor power converters with integrated low dropout regulator,” IEEE International Symposium on Circuits and Systems, 2001, pp. 293-296. [51] Tamal Das, et al., “Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple,” International Conference on VLSI Design, 2009, pp. 181-186. [52] Feng Su, et al., “Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation,” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1112-1120, Apr. 2009. [53] Yogesh Ramadass et al., “A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.208-209, Feb. 2010. [54] Behzad Razavi, Design of Analog CMOS Integrated Circuits. McGraw Hill, 2001. [55] R. Jacob Baker, CMOS: Circuit design, layout, and simulation. Wiley-IEEE Press, 2011. [56] A. S. Sedra and K. C. Smith, Microelectronic Circuits. Oxford University Press, 2004. [57] Airong Liu, et al., “Low Voltage Low Power Class-AB OTA with Negative Resistance Load,” International Conference on Communications, Circuits and Systems, 2006, pp. 2251-2254. [58] W.-J. Huang, et al., “Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array,” IET Circuits, Devices & Systems, vol. 2, no. 3, pp. 306-316, Mar. 2007. [59] Dae-Seok Byeon, et al., “An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology,” IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 46-47.
本論文為利用標準CMOS邏輯製程設計的非揮發性記憶體元件設計其周邊電路,記憶體陣列為8 bits,使其能完成寫入、抹除、讀取和驗證的功能。周邊電路包含位址選擇電路、字元線電壓驅動電路、位元線電壓驅動電路、源極線電壓驅動電路、電流感測放大器、驗證電路和輸出級電路。由於操作電壓會高於標準電壓,因此這些電路必須特別耐高壓,所以開發特別耐壓電路。電路設計完成模擬和量測,量測結果顯示記憶體寫入和抹除時間需要10 ms,而讀取時間不管是切換位址或是讀取單一記憶體元件都能在11 ns內完成。
另外,由於記憶體元件的操作條件需要很多種不同電壓,所以也設計了降壓器電路。降壓器電路架構是使用切換電容式降壓器,在大幅降壓的情況下比低壓降線性穩壓器的效率還高。此電路也完成模擬與量測,此降壓器可從5 V降壓到1.8 V、1.2 V和1.0 V,在1.8 V最大負載電流為44mA而最大效率為68.6%,在1.2 V最大負載電流為79mA而最大效率為67.9%,在1.0 V最大負載電流為78mA而最大效率為54.8%。

In recent years, embedded non-volatile memories are used in various systems. However, due to compatibility of processes, memory chips and the other functional chips are fabricated separately. If the memories can be integrated in the same chip with analog and digital circuits, the single chip is usually referred as SOC (system-on-a-chip). In the mean time, the cost and fabrication time can be reduced.
The thesis presents the design of the peripheral circuits for the CMOS-based non-volatile memory cells. The circuits perform program, erase, read and verify for the 8-bit memory array. These include the address decoder, word line driver, bit line driver, source line driver, current sense amplifier, verifying circuit and output stage. Specifically some of these circuits require high-voltage tolerant abilities owing to the operating voltages for program and erase higher than the standard voltage. The peripheral circuit was designed and fabricated. The measurement results show that the memory cells can be programmed and erased within 10 milliseconds and the time of reading for any address is within 11 nanoseconds.
Furthermore, the operation of the memory cells needs different bias voltages. Thus, the DC-DC step-down converter was designed. By comparison with low-dropout regulator (LDO), the DC-DC step-down converter employing the switched-capacitor structure can enhance the power efficiency for high voltage conversion ratio which is defined as Vout/Vin, such as 5 V to 1.8 V, 1.2 V and 1 V. The circuit was also designed and fabricated. The measurement results demonstrate the maximum load current is 44 mA with the peak efficiency of 68.6% for 1.8 V output. By switching to the 1.2 V and 1 V modes, the maximum load currents are 79 mA and 78 mA with the peak efficiencies of 67.9% and 54.8%, respectively.
其他識別: U0005-2607201215490600
Appears in Collections:電機工程學系所

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.