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The Fully CMOS Compatible Multiple-Time-Programmable Memory Circuits and Switched-Capacitor DC-DC Converter Design
|關鍵字:||非揮發性記憶體;non-volatile memory;多次性寫入;高電壓驅動電路;高電壓隔離電路;切換電容式降壓器;multiple-time-programmable;high voltage driver;high voltage isolation;switched-capacitor DC-DC converter||出版社:||電機工程學系所||引用:|| Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded nonvolatile memory applications,” Symp. VLSI Tech. Dig., 2003, pp.93-94.  Hsiu-Fen Chou, et al., “Comprehensive study on a novel bidirectional tunneling program/erase NOR-type (BiNOR) 3-D flash memory cell,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1386-1393, Jul. 2001.  Chang Sean, et al., “New buried bit-line NAND (Bi-NAND) Flash memory for data storage,” Symp. VLSI Tech. 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Dae-Seok Byeon, et al., “An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology,” IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 46-47.||摘要:||
本論文為利用標準CMOS邏輯製程設計的非揮發性記憶體元件設計其周邊電路，記憶體陣列為8 bits，使其能完成寫入、抹除、讀取和驗證的功能。周邊電路包含位址選擇電路、字元線電壓驅動電路、位元線電壓驅動電路、源極線電壓驅動電路、電流感測放大器、驗證電路和輸出級電路。由於操作電壓會高於標準電壓，因此這些電路必須特別耐高壓，所以開發特別耐壓電路。電路設計完成模擬和量測，量測結果顯示記憶體寫入和抹除時間需要10 ms，而讀取時間不管是切換位址或是讀取單一記憶體元件都能在11 ns內完成。
另外，由於記憶體元件的操作條件需要很多種不同電壓，所以也設計了降壓器電路。降壓器電路架構是使用切換電容式降壓器，在大幅降壓的情況下比低壓降線性穩壓器的效率還高。此電路也完成模擬與量測，此降壓器可從5 V降壓到1.8 V、1.2 V和1.0 V，在1.8 V最大負載電流為44mA而最大效率為68.6%，在1.2 V最大負載電流為79mA而最大效率為67.9%，在1.0 V最大負載電流為78mA而最大效率為54.8%。
In recent years, embedded non-volatile memories are used in various systems. However, due to compatibility of processes, memory chips and the other functional chips are fabricated separately. If the memories can be integrated in the same chip with analog and digital circuits, the single chip is usually referred as SOC (system-on-a-chip). In the mean time, the cost and fabrication time can be reduced.
The thesis presents the design of the peripheral circuits for the CMOS-based non-volatile memory cells. The circuits perform program, erase, read and verify for the 8-bit memory array. These include the address decoder, word line driver, bit line driver, source line driver, current sense amplifier, verifying circuit and output stage. Specifically some of these circuits require high-voltage tolerant abilities owing to the operating voltages for program and erase higher than the standard voltage. The peripheral circuit was designed and fabricated. The measurement results show that the memory cells can be programmed and erased within 10 milliseconds and the time of reading for any address is within 11 nanoseconds.
Furthermore, the operation of the memory cells needs different bias voltages. Thus, the DC-DC step-down converter was designed. By comparison with low-dropout regulator (LDO), the DC-DC step-down converter employing the switched-capacitor structure can enhance the power efficiency for high voltage conversion ratio which is defined as Vout/Vin, such as 5 V to 1.8 V, 1.2 V and 1 V. The circuit was also designed and fabricated. The measurement results demonstrate the maximum load current is 44 mA with the peak efficiency of 68.6% for 1.8 V output. By switching to the 1.2 V and 1 V modes, the maximum load currents are 79 mA and 78 mA with the peak efficiencies of 67.9% and 54.8%, respectively.
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