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Chip Design for the Peripheral Circuits of Embedded Differential Multi-Time-Programmable Memories Including Switched-Capacitor Step-Down Converters
|關鍵字:||降壓器;Peripheral Circuits;記憶體週邊電路;切換式電容;差動型;記憶體;Differential;Switched-Capacitor;Step-Down;MTP||出版社:||電機工程學系所||引用:|| N. N. Mojumder, K. Roy, and D. W. Abraham, “Thermoelectric Spin-Transfer Torque MRAM With Fast Bidirectional Writing Using Magnonic Current,” IEEE Trans. Magnetics, vol. 49, no. 1, pp. 483-488, Jan. 2013.  Y. Lakys, W. S. Zhao, J.-O. Klein, and C. Chappert, “Hardening Techniques for MRAM-Based Nonvolatile Latches and Logic,” IEEE Trans. Nuclear Science, vol. 59, no. 4, pp. 1136-1141, Aug. 2012.  M. Qaz, M. Clinton, S. Bartling, A. P. Chandrakasan, “A Low-Voltage 1Mb FeRAM in 0.13μm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin in Scaled CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 208-210, Feb. 2011.  D. Takashima, Y. Nagadomi, and T. Ozaki, “A 100 MHz Ladder FeRAM Design with Capacitance-Coupled-Bitline (CCB) Cell,” IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 681-689, March 2011.  Y.-C. Chen and H. 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此外，由於在操作上需要使用多種電壓，因此另外設計降壓穩壓電路。在架構上，使用切換電容式降壓器，也就是電容串並聯組合讓輸出穩定在一固定值，且讓參考電壓改變可以增加負載電流的大小，以減少漣波，運用TSMC 0.25μm HV CMOS製程設計的模擬結果顯示，此降壓器可從5 V降壓到1.2 V和1.0 V，在1.2 V最大負載電流為90mA而最大效率為60.3%，在1.0 V最大負載電流為120mA而最大效率為52%。
In the development of systems-on-chip technologies, the CMOS embedded non-volatile memories usually need extra process steps. However, those without extra processes are also possible. The former is suitable for median memory capacities with the higher cost. The latter is appropriate for small memory capacities. If the systems do not require large memory capacities, the technique without the extra processes can be applied for cost and fabrication time reduction.
In this thesis, the peripheral circuits are designed for differential Multi-Time-Programmable (MTP) non-volatile memories, which were recently proposed by our laboratory using the standard 0.18μm CMOS process. Those peripheral circuits include the address buffer and decoder, word line driver, bit line driver, control line driver, current sense amplifier, verify circuit and output stage in order to program, erase, and read, as well as verify the differential MTP memory array. However, the special memory cells need the voltage higher than the standard supply voltage and the negative voltage during program and erase. Thus, the special voltage tolerable circuits are required. After the peripheral circuits were designed and simulated, they were fabricated and measured successfully. The measurement results show that the memory cells can be programmed and erased within 1 millisecond, and the time to randomly read any memory cells is within 11.4 nanoseconds.
Besides, because various bias voltages are required, the step-down regulator was also designed. The converters use the switched-capacitor structure which is combination of capacitors in parallel and series to generate constant step-down output voltages. In addition, the loading current can be increased and the ripple can be decreased by changing the reference voltages. The regulator producing 1V and 1.2V was designed, simulated and under fabrication using the TSMC 0.25μm HV CMOS process. The simulation results demonstrate the efficiencies of 60.3% for the output of 1.2 V and 52% for that of 1 V with the loading currents of 90mA and 120mA, respectively.
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