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dc.contributorHongchin Linen_US
dc.contributor.authorWu, Chia-Youen_US
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dc.description.abstract在系統晶片的發展上,嵌入式CMOS製程之非揮發性記憶體,通常需要額外製程,然而完全不需要額外製程,也是有可能的,前者適合中等記憶體容量且成本較高,後者適合小記憶體容量。若系統中非揮發性記憶體不需要大容量,則可使用不需要額外製程的做法,來減少製作時間與成本。 本論文運用本實驗室最近開發以標準0.18μm CMOS製程,且不需要額外光罩與製程步驟的差動型可多次寫入非揮發性記憶體元件,設計其週邊電路,包括位址選擇與緩衝電路、字元線電壓驅動電路、位元線電壓驅動電路、控制閘極線電壓驅動電路、電流感測放大器、驗證電路和輸出級電路,以便對記憶體陣列做寫入、抹除、讀取與驗證的功能。但是因為此元件的寫入、抹除操作條件電壓高於製程耐壓,且有負電壓,所以需要設計特殊的耐壓電路,經過完整的模擬並下線,最後成功量測完成。在量測時記憶體寫入和抹除時間能在1ms完成,而記憶體元件隨機讀取時間能在11.4ns內完成。 此外,由於在操作上需要使用多種電壓,因此另外設計降壓穩壓電路。在架構上,使用切換電容式降壓器,也就是電容串並聯組合讓輸出穩定在一固定值,且讓參考電壓改變可以增加負載電流的大小,以減少漣波,運用TSMC 0.25μm HV CMOS製程設計的模擬結果顯示,此降壓器可從5 V降壓到1.2 V和1.0 V,在1.2 V最大負載電流為90mA而最大效率為60.3%,在1.0 V最大負載電流為120mA而最大效率為52%。zh_TW
dc.description.abstractIn the development of systems-on-chip technologies, the CMOS embedded non-volatile memories usually need extra process steps. However, those without extra processes are also possible. The former is suitable for median memory capacities with the higher cost. The latter is appropriate for small memory capacities. If the systems do not require large memory capacities, the technique without the extra processes can be applied for cost and fabrication time reduction. In this thesis, the peripheral circuits are designed for differential Multi-Time-Programmable (MTP) non-volatile memories, which were recently proposed by our laboratory using the standard 0.18μm CMOS process. Those peripheral circuits include the address buffer and decoder, word line driver, bit line driver, control line driver, current sense amplifier, verify circuit and output stage in order to program, erase, and read, as well as verify the differential MTP memory array. However, the special memory cells need the voltage higher than the standard supply voltage and the negative voltage during program and erase. Thus, the special voltage tolerable circuits are required. After the peripheral circuits were designed and simulated, they were fabricated and measured successfully. The measurement results show that the memory cells can be programmed and erased within 1 millisecond, and the time to randomly read any memory cells is within 11.4 nanoseconds. Besides, because various bias voltages are required, the step-down regulator was also designed. The converters use the switched-capacitor structure which is combination of capacitors in parallel and series to generate constant step-down output voltages. In addition, the loading current can be increased and the ripple can be decreased by changing the reference voltages. The regulator producing 1V and 1.2V was designed, simulated and under fabrication using the TSMC 0.25μm HV CMOS process. The simulation results demonstrate the efficiencies of 60.3% for the output of 1.2 V and 52% for that of 1 V with the loading currents of 90mA and 120mA, respectively.en_US
dc.description.tableofcontents誌謝 I 摘要 II Abstract III 目次 IV 圖目次 VII 表目次 X 第一章 序論 1 1.1 前言 1 1.2 記憶體介紹 2 1.3 記憶體週邊電路系統 3 1.3.1 控制訊號產生電路 4 1.3.2 解碼電路 4 1.3.3 電壓驅動電路 5 1.3.4 讀取電路 5 1.3.5 驗證電路 5 1.3.6 電壓源產生電路 5 降壓器種類 6 控制電路之頻率響應補償 9 1.4 研究動機 11 1.5 論文大綱 12 第二章 嵌入式可多次寫入差動型非揮發性記憶體之架構與研究 13 2.1 MTP記憶體元件結構 13 2.2 MTP記憶體操作原理 15 2.2.1 寫入操作原理 15 2.2.2 抹除操作原理 16 2.2.3 讀取操作原理 16 2.3 記憶體特性分析與量測結果 17 2.3.1 初始特性分析與量測結果 17 2.3.2 寫入特性分析與量測結果 18 2.3.3 抹除特性分析與量測結果 18 2.3.4 寫入與抹除特性之電流差異 19 第三章 嵌入式差動型MTP記憶體之週邊電路 20 3.1 記憶體週邊電路架構 20 3.2 記憶體陣列 21 3.3 記憶體週邊電路 23 3.3.1 位址緩衝與解碼電路 23 3.3.2 字元線電壓選擇電路與驅動電路 24 3.3.3 控制閘極線電壓驅動電路 25 3.3.4 位元線電壓驅動電路 27 3.3.5 負電壓隔離與輸出級電路 30 3.3.6 電流感測放大器與驗證電路 31 讀取動作 32 抹除前或寫入後資料驗證階段之動作 37 3.4 抹除與寫入動作流程 38 3.5 讀取、抹除與寫入之模擬結果 39 3.5.1 抹除0與寫入1之模擬結果 39 3.5.2 抹除1與寫入0之模擬結果 40 3.5.3 重複讀取動作之模擬結果 40 3.6 電路佈局與量測 42 3.6.1 電路佈局與下線晶片圖 42 3.6.2 量測架構與儀器 43 3.6.3 量測記憶體讀取、抹除及寫入操作 44 3.6.4 抹除0與全寫入1動作量測 45 3.6.5 抹除1與全寫入0動作量測 47 3.6.6 抹除與寫入動作量測 49 3.6.7 交換位址時讀取動作量測 51 3.6.8 量測結果規格表 51 第四章 改良式四相位切換電容式降壓器 52 4.1 改良式降壓器之架構與原理 52 4.2 降壓器主要架構 53 4.2.1 切換電容式電路與控制時脈 53 4.2.2 理想最大效率分析 58 4.3 巢狀補償之誤差放大器 59 4.4 遲滯比較器 62 4.5 啟始電路與偏壓電路 63 4.6 輸入訊號和控制訊號緩衝器 64 4.7 電路模擬結果 65 4.7.1 電路開迴路增益 65 4.7.2 電路閉迴路增益 68 4.7.3 遲滯比較器之控制與遲滯範圍 70 4.7.4 電路輸出電壓、效率與漣波值 71 4.8 電路佈局與下線 76 4.8.1 電路佈局與下線晶片圖 76 4.8.2 量測架構與儀器 77 4.9 整體電路效能與比較 78 第五章 總結與未來工作 79 參考文獻 80zh_TW
dc.subjectPeripheral Circuitsen_US
dc.titleChip Design for the Peripheral Circuits of Embedded Differential Multi-Time-Programmable Memories Including Switched-Capacitor Step-Down Convertersen_US
dc.typeThesis and Dissertationzh_TW
item.openairetypeThesis and Dissertation-
item.fulltextno fulltext-
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