Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9255
標題: 嵌入式差動型MTP記憶體週邊電路含切換式電容降壓器晶片設計
Chip Design for the Peripheral Circuits of Embedded Differential Multi-Time-Programmable Memories Including Switched-Capacitor Step-Down Converters
作者: 吳嘉祐
Wu, Chia-You
關鍵字: 降壓器;Peripheral Circuits;記憶體週邊電路;切換式電容;差動型;記憶體;Differential;Switched-Capacitor;Step-Down;MTP
出版社: 電機工程學系所
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摘要: 
在系統晶片的發展上,嵌入式CMOS製程之非揮發性記憶體,通常需要額外製程,然而完全不需要額外製程,也是有可能的,前者適合中等記憶體容量且成本較高,後者適合小記憶體容量。若系統中非揮發性記憶體不需要大容量,則可使用不需要額外製程的做法,來減少製作時間與成本。
本論文運用本實驗室最近開發以標準0.18μm CMOS製程,且不需要額外光罩與製程步驟的差動型可多次寫入非揮發性記憶體元件,設計其週邊電路,包括位址選擇與緩衝電路、字元線電壓驅動電路、位元線電壓驅動電路、控制閘極線電壓驅動電路、電流感測放大器、驗證電路和輸出級電路,以便對記憶體陣列做寫入、抹除、讀取與驗證的功能。但是因為此元件的寫入、抹除操作條件電壓高於製程耐壓,且有負電壓,所以需要設計特殊的耐壓電路,經過完整的模擬並下線,最後成功量測完成。在量測時記憶體寫入和抹除時間能在1ms完成,而記憶體元件隨機讀取時間能在11.4ns內完成。
此外,由於在操作上需要使用多種電壓,因此另外設計降壓穩壓電路。在架構上,使用切換電容式降壓器,也就是電容串並聯組合讓輸出穩定在一固定值,且讓參考電壓改變可以增加負載電流的大小,以減少漣波,運用TSMC 0.25μm HV CMOS製程設計的模擬結果顯示,此降壓器可從5 V降壓到1.2 V和1.0 V,在1.2 V最大負載電流為90mA而最大效率為60.3%,在1.0 V最大負載電流為120mA而最大效率為52%。

In the development of systems-on-chip technologies, the CMOS embedded non-volatile memories usually need extra process steps. However, those without extra processes are also possible. The former is suitable for median memory capacities with the higher cost. The latter is appropriate for small memory capacities. If the systems do not require large memory capacities, the technique without the extra processes can be applied for cost and fabrication time reduction.
In this thesis, the peripheral circuits are designed for differential Multi-Time-Programmable (MTP) non-volatile memories, which were recently proposed by our laboratory using the standard 0.18μm CMOS process. Those peripheral circuits include the address buffer and decoder, word line driver, bit line driver, control line driver, current sense amplifier, verify circuit and output stage in order to program, erase, and read, as well as verify the differential MTP memory array. However, the special memory cells need the voltage higher than the standard supply voltage and the negative voltage during program and erase. Thus, the special voltage tolerable circuits are required. After the peripheral circuits were designed and simulated, they were fabricated and measured successfully. The measurement results show that the memory cells can be programmed and erased within 1 millisecond, and the time to randomly read any memory cells is within 11.4 nanoseconds.
Besides, because various bias voltages are required, the step-down regulator was also designed. The converters use the switched-capacitor structure which is combination of capacitors in parallel and series to generate constant step-down output voltages. In addition, the loading current can be increased and the ripple can be decreased by changing the reference voltages. The regulator producing 1V and 1.2V was designed, simulated and under fabrication using the TSMC 0.25μm HV CMOS process. The simulation results demonstrate the efficiencies of 60.3% for the output of 1.2 V and 52% for that of 1 V with the loading currents of 90mA and 120mA, respectively.
URI: http://hdl.handle.net/11455/9255
其他識別: U0005-2508201322323500
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