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dc.contributorChung-Bin Wuen_US
dc.contributor.authorChou, Yu-Linen_US
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dc.description.abstract本論文提出一個適用於VP8以及H.264/AVC多重視訊標準之硬體共享區塊消除濾波器設計。首先,我們重新整理原始視訊標準中區塊消除濾波器之相同點並提出一套適用於VP8以及H.264/AVC之硬體架構以達到硬體共享進而減少硬體面積。為了更進一步降低運算複雜度,我們,犧牲少許影像畫質,另外提出了一高度硬體共享之架構設計以獲得最大硬體共享。另一方面,為了節省區塊效應消除濾波器運算中所使用的記憶體空間,我們提出與移動補償電路之記憶體共享架構,利用重新安排區塊邊界的濾波器運算順序,進而有效配置記憶體存取並有效達記憶體共享。 實驗結果顯示,我們提出的高度硬體共享之架構設計比個別實現兩組視訊標準節省了63.3%之位移器,77.4%之加法器,以及100%之乘法器。整體而言,於VP8解碼器中,PSNR平均降低不到1%。最後,我們採用TSMC 0.18 μm cell library的製程進行電路實作,結果顯示本架構操作在130 MHz 的頻率下可完成Full HD 1080P@30fps的區塊消除濾波器的運算而Gate Count為43.2K。由結果顯示,本電路,可適用於VP8以及H.264/AVC視訊標準之編碼器與解碼器。zh_TW
dc.description.abstractIn this thesis, a hardware sharing architecture to perform the multi-standard deblocking filter that support VP8 and H.264/AVC is proposed. First, a reorganization of deblocking filter is used to derive a common architecture which is suitable for H.264/AVC and VP8. The proposed design is then reused for the whole filtering. To further reduce the computational complexity, highly sharing architecture is also presented. In order to save the size of the on-chip memory, a memory sharing architecture of the deblocking filter and motion compensation is introduced. We also reorganize the processing order of filtering to reduce the total on-chip memory size. According to the experimental results, the adopted hardware sharing architecture saves 63.3% of shifters, 77.4% of adders and 100% of multipliers totally. The overall PSNR drops less than 1% on the VP8 decoder for low complexity applications. Finally, a hardware implementation using TSMC 0.18 μm cell library is performed. The clock frequency of the proposed hardware is working at 130 MHz to perform deblocking filter for supporting Full HD 1080P@30fps. The implementation results show that the gate count of this architecture adopted on VP8 and H.264/AVC video codec system is 43.2K.en_US
dc.description.tableofcontentsChapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Overview 4 2.1 Video Coding Standard 4 2.2 Video Coding Concepts 5 2.3 Introduction to H.264/AVC Video Standard 7 2.4 Introduction to VP8 Video Standard 9 2.5 Introduction to Deblocking Filter 12 2.6 Related Work 13 Chapter 3 Deblocking Filter Algorithm 24 3.1 H.264 Deblocking Filter 24 3.1.1 Processing Order of Deblocking filter 25 3.1.2 Boundary Strength Decision 26 3.1.3 Mode Decision 28 3.1.4 Normal Filter 30 3.1.5 Strong Filter 32 3.2 VP8 Deblocking Filter 33 3.2.1 Normal Filter 33 3.2.2 Simple Filter 34 3.3 Proposed Deblocking Algorithm 35 3.3.1 Deblocking Filter Reorganization 35 3.3.2 Deblocking Filter for Low Complexity Applications 40 3.4 Experimental Result 41 Chapter 4 Architecture Design of Deblocking Filter 50 4.1 Architecture Overview 50 4.2 Memory Allocation 51 4.3 Processing Order of Deblocking Filter 55 4.4 Proposed Architecture of Filtering 61 4.5 Pipelined Architecture 64 4.6 Implementation of VLSI Architecture 67 4.7 Synthesis Results 69 Chapter 5 Conclusion 71 5.1 Conclusion 71 5.2 Future Work 71 Reference 72 Biography 76zh_TW
dc.subjectDeblocking Filteren_US
dc.subjectHardware Sharing Architectureen_US
dc.titleA Hardware Sharing Architecture of Deblocking Filter for VP8 and H.264/AVC Video Codingen_US
dc.typeThesis and Dissertationzh_TW
item.openairetypeThesis and Dissertation-
item.fulltextno fulltext-
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