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Optimized Quantization Analysis for LDPC Decoders in Multi-Level Flash Memories
|關鍵字:||多階層快閃記憶體;Multi-Level Flash Memories;低密度奇偶查核碼;LDPC||出版社:||電機工程學系所||引用:||Carla Lay, “System Benefits of EZ NAND/ Enhanced ClearNANDTM Flash,” Micron Technology Inc., pp. 6-24, August 11, 2011. “SmartNAND™ Flash,” Toshiba Technology Inc., 2011. Aaron Thean and Jean-Pierre Leburton, “Flash memory: towards single-electronics,” IEEE Potentials Magazines, vol. 21, Oct. 2002. “Samsung NAND Flash Memory Memory Product &Technology Division 2000.3.15,” Samsung Technology Inc., Mar. 2000. “FLASH Technology Samsung Electronics 2004. 9. 8,” Samsung Technology Inc., Sep., 2004. D. J. C. MacKay and R. M. Neal, “Near Shannon limit performance of low density parity check codes,” Electron. Lett., vol. 32, no. 18, pp. 1645-1646, Aug. 1996. N. Wiberg, “codes and decoding on general graphs,” Ph.D. thesis, Linkoping University, Sweden, 1996. D. J. C. MacKay, “Gallager codes that are better than turbo codes,” in Proc. 36th Allerton Conf. Communications, Control, and Computing, Sept. 1998. E. M. Kurtas, A. V. Kuznetsov, I. Djurdjevic, “System perspectives for the application of structured LDPC codes to data storage devices,” IEEE Trans. On Magnetics, vol. 42, no. 2, Feb. 2006. L. Chen, J. Xu, I. Djurdjevic, and S. Lin, “Near Shannon limit quasi-cyclic low density parity check codes,” IEEE Trans. on Communications, vol. 52, no.7, July 2004. J. Membe and J. M. F. Moura, “Partition-and-shift LDPC codes,” IEEE Transactions on Magnetics, vol. 41, no. 10, Oct. 2005. F. R. Kshischang and B. J. Frey, “Iterative decoding of compound codes by probability propagation in graphical models,” IEEE Journal on Selected Areas in Communications, vol. 16, pp. 219-230, Feb. 1998. 王泓人, ”Design of Low Power Dual-Path PS-LDPC Decoder,” 碩士論文,中興大學,電機所,中華民國九十八年七月. J. Hagenauer, E. Offer, L. Papke, “Iterative decoding of binary block and convolutional codes,” IEEE Trans. On Inform. Theory, vol. 42, no. 2, pp. 429-445, March 1996. J. Zang, M. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, Feb. 2005. D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Proc. IEEE Workshop on SiPS., pp. 107-112, Oct. 2004. K. Zhang, X. Huang, Z. Wang, “High-Throughput layered decoder implementation for quasi-cyclic LDPC codes,” IEEE JSAC, vol. 27, no. 6, Aug. 2009. Shu-Cheng Chou, Mong-Kai Ku and Chia-Yu Lin, “Switching Activity Reducing Layered Decoding Algorithm for LDPC Codes,” IEEE Circuits and Systems, pp.528-531, 18-21 May 2008. 林學群, “Circuit Design of Low Error-Floor LDPC Decoders Using R-LMSA with Post-Processing Technique for Wireless Systems,” 碩士論文,中興大學,電機所,中華民國一百零一年七月. “Micron 64Gb, 128Gb, 256Gb Asynchronous/ Synchronous NAND,” Micron Technology Inc., 2008. Yuu Maeda and Haruhiko Kaneko, “Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes,” 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 367-375 2009. John R. Barry, Edward A. Lee, David G. Messerschmitt, Digital Communication, 3rd ed.: Kluwer Academic, Sep. 2003. Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen and Chih-Tsun Huang, “Reliability Analysis and Improvement for Multi-Level Non-Volatile Memories with Soft Information,” IEEE 2011 Design Automation Conference (DAC), pp.753-758, 5–10 June 2011. Guiqiang Dong, Ningde Xie, and Tong Zhang, “On the Use of Soft-Decision Error-Correction Codes in NAND Flash Memory,” IEEE Transactions on Circuits and Systems, vol. 58, no. 2, pp.429-439, Feb. 2011. Seungjune Jeon, Euiseok Hwang, B. V. K. Vijaya Kumar and Michael K. Cheng, “LDPC Codes for Memory Systems with Scrubbing,” IEEE Global Telecommunications Conference, pp. 1-6, 2010. Jiadong Wang, Thomas Courtade, Hari Shankar and Richard D. Wesel, “Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization,” IEEE Global Telecommunications Conference, pp. 1-6, 2011. Jiadong Wang, Guiqiang Dong, Tong Zhang and Richard Wesel, “Mutual-Information Optimized Quantization for LDPC Decoding of Accurately Modeled Flash Data,” Cornell University Library, 7 Feb. 2012.||摘要:||
本論文提出應用於快閃記憶體系統之低錯誤基數 Reset Layer Min Sum Algorithm (R-LMSA) LDPC 解碼器的最佳量化分析。本主題有幾個主要的重點: <1> 建構快閃記憶體多階層儲存單位的model，其中包括臨界電壓值平均值、Sigma值、功率比例比值的建立與推導。<2>採用臨界電壓與Q Ratio，來產生最佳感應電壓值，以及得出每個State在高位元LLR值和低位元LLR值，以便LDPC解碼。<3>採用快閃記憶體的單階層儲存單位1 Sensing Level和3 Sensing Levels與多階層儲存單位3 Sensing Levels、6 Sensing Levels 和7 Sensing Levels的模型，來進行浮點數和R-LMSA LDPC解碼效能最佳量化分析與比較，進而得出最佳Q-Ratio 和最佳LLR數值量化的位元數。
其中，決定最佳化Q Ratio，此論文搜尋Q Ratio為1, 1/2, 5/8, 11/16, 3/4, 13/16, 7/8，並進行LLR運算，以便使得浮點數LDPC解碼能力達到最好。因為R-LMSA的演算法可以改善錯誤基數(Error floor)現象，提升LDPC解碼能力，所以運用其尋找最佳化的Q Ratio值，以作為未來硬體實作時的依據。我們利用查表法取得LLR數值量，用以模擬得到單階層儲存單位1 Sensing Level和3 Sensing Levels與多階層儲存單位3 Sensing Levels、6 Sensing Levels 和7 Sensing Levels的最佳bit error rate (BER)值，並決定最佳位元數，使結果趨近至浮點數解碼的BER值，預期就可以有效降低硬體複雜度。
In this thesis, the optimized quantization for multi-level flash systems is analyzed using a low error-floor low density parity check (LDPC) decoder with reset layer min sum algorithm (R-LMSA). The three major contributions include (1) The model of multi-level NAND flash memories is developed, such as the averages of threshold voltages, standard deviations (σ), and power ratios. (2) The sensing voltages are determined using the average threshold voltages and the Q ratio. Thus, the optimized log likelihood ratios (LLR) of the most significant bit (MSB) and the least significant bit (LSB) are obtained for LDPC calculations. (3) The floating-point R-LMSA LDPC decoding performance with the optimized quantization and comparison are reported for the single-level cell with one and three sensing levels, as well as the multi-level cell with three, six, and seven sensing levels. Therefore, the optimized Q-Ratio and quantization are obtained.
To determine the optimized Q ratio to achieve the best LDPC decoding performance, Q ratios of 1, 1/2, 5/8, 11/16, 3/4, 13/16, 7/8 were investigated and the corresponding LLR values were calculated. Since R-LMSA can alleviate the phenomenon of error floors to improve the performance of LDPC, it was employed to find the optimized Q ratio. We utilized look-up-table method to obtain the LLR values and simulated the bit error rate (BER) curves to determine the most efficient quantization bits for the single-level cell with one and three sensing levels, as well as the multi-level cell with three, six, and seven sensing levels. Through this study, we have obtained the curves close enough to those calculated by the floating point method in order to reduce the hardware complexity during implementation.
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