Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9288
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dc.contributor林泓均zh_TW
dc.contributor.author吳柏昇zh_TW
dc.contributor.authorWu, Po-Shengen_US
dc.contributor.other電機工程學系所zh_TW
dc.date2012en_US
dc.date.accessioned2014-06-06T06:43:00Z-
dc.date.available2014-06-06T06:43:00Z-
dc.identifierU0005-0811201222391600en_US
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dc.identifier.urihttp://hdl.handle.net/11455/9288-
dc.description.abstract本論文提出應用於快閃記憶體系統之低錯誤基數 Reset Layer Min Sum Algorithm (R-LMSA) LDPC 解碼器的最佳量化分析。本主題有幾個主要的重點: <1> 建構快閃記憶體多階層儲存單位的model,其中包括臨界電壓值平均值、Sigma值、功率比例比值的建立與推導。<2>採用臨界電壓與Q Ratio,來產生最佳感應電壓值,以及得出每個State在高位元LLR值和低位元LLR值,以便LDPC解碼。<3>採用快閃記憶體的單階層儲存單位1 Sensing Level和3 Sensing Levels與多階層儲存單位3 Sensing Levels、6 Sensing Levels 和7 Sensing Levels的模型,來進行浮點數和R-LMSA LDPC解碼效能最佳量化分析與比較,進而得出最佳Q-Ratio 和最佳LLR數值量化的位元數。 其中,決定最佳化Q Ratio,此論文搜尋Q Ratio為1, 1/2, 5/8, 11/16, 3/4, 13/16, 7/8,並進行LLR運算,以便使得浮點數LDPC解碼能力達到最好。因為R-LMSA的演算法可以改善錯誤基數(Error floor)現象,提升LDPC解碼能力,所以運用其尋找最佳化的Q Ratio值,以作為未來硬體實作時的依據。我們利用查表法取得LLR數值量,用以模擬得到單階層儲存單位1 Sensing Level和3 Sensing Levels與多階層儲存單位3 Sensing Levels、6 Sensing Levels 和7 Sensing Levels的最佳bit error rate (BER)值,並決定最佳位元數,使結果趨近至浮點數解碼的BER值,預期就可以有效降低硬體複雜度。zh_TW
dc.description.abstractIn this thesis, the optimized quantization for multi-level flash systems is analyzed using a low error-floor low density parity check (LDPC) decoder with reset layer min sum algorithm (R-LMSA). The three major contributions include (1) The model of multi-level NAND flash memories is developed, such as the averages of threshold voltages, standard deviations (σ), and power ratios. (2) The sensing voltages are determined using the average threshold voltages and the Q ratio. Thus, the optimized log likelihood ratios (LLR) of the most significant bit (MSB) and the least significant bit (LSB) are obtained for LDPC calculations. (3) The floating-point R-LMSA LDPC decoding performance with the optimized quantization and comparison are reported for the single-level cell with one and three sensing levels, as well as the multi-level cell with three, six, and seven sensing levels. Therefore, the optimized Q-Ratio and quantization are obtained. To determine the optimized Q ratio to achieve the best LDPC decoding performance, Q ratios of 1, 1/2, 5/8, 11/16, 3/4, 13/16, 7/8 were investigated and the corresponding LLR values were calculated. Since R-LMSA can alleviate the phenomenon of error floors to improve the performance of LDPC, it was employed to find the optimized Q ratio. We utilized look-up-table method to obtain the LLR values and simulated the bit error rate (BER) curves to determine the most efficient quantization bits for the single-level cell with one and three sensing levels, as well as the multi-level cell with three, six, and seven sensing levels. Through this study, we have obtained the curves close enough to those calculated by the floating point method in order to reduce the hardware complexity during implementation.en_US
dc.description.tableofcontents誌謝i 中文摘要ii Abstractiii 目錄iv 圖目錄vi 表目錄viii 第一章 序論1 1.1 快閃記憶體系統及錯誤更正碼簡介1 1.2 研究動機2 1.3 論文架構3 第二章 記憶體簡介4 2.1 快閃記憶體歷史溯源4 2.2 快閃記憶體操作原理5 2.2.1 Program (寫入)原理6 2.2.2 Erase (抹除)原理7 2.2.3 Read (讀取)原理8 2.3 快閃記憶體資料產生錯誤原因11 第三章 低密度奇偶查核碼解碼簡介14 3.1 低密度奇偶查核碼基本概念14 3.1.1 Tanner Graph14 3.1.2 LDPC Code之定義14 3.2 結構化低密度奇偶查核碼15 3.2.1 QC-LDPC Code16 3.2.2 分割轉移矩陣 PS-LDPC Code17 3.3 低密度奇偶查核碼之解碼19 3.3.1 Message Passing Algorithm20 3.3.2 Sum-Product Algorithm 21 3.4 低密度奇偶查核碼解碼之演算法24 3.4.1 Log Sum-Product Algorithm24 3.4.2 Min-Sum Algorithm26 3.4.3 Layered Min Sum Algorithm27 3.5 降低錯誤基數R-LMSA29 第四章 運用低密度奇偶查核矩陣於快閃記憶體之方法31 4.1 分割轉移矩陣效能分析31 4.2 NAND 快閃記憶體多階層儲存單位模型建立33 4.2.1 信噪比與臨界電壓值分佈標準差推導關係34 4.2.2 使用低密度奇偶檢查碼和信噪比關係35 4.3 LOG LIKELIHOOD RATIO37 4.3.1 Log Likelihood Ratio機率算法37 4.3.2 數值量化之觀念39 4.3.3 數值量化擴充之概念40 4.4 使用多階層SENSING LEVEL來讀取資料41 4.5 感應電壓邊界介紹和LLR TABLE44 4.5.1 多階層Sensing Boundary設定44 4.5.2 Sensing Level劃分不同區域和LLR Table的關係47 4.6 SIGMA RATIO介紹49 第五章 效能模擬及分析52 5.1 SENSING LEVEL 定義52 5.2 最佳 SENSING LEVEL WITH Q RATIO53 5.2.1 SLC Sensing Level 模擬53 5.2.2 MLC Sensing Level 模擬55 5.2.3 與未編解碼之SLC/ MLC 效能比較57 5.3 運用R-LMSA 之最佳量化分析58 5.3.1 SLC 1Read58 5.3.2 SLC 3Read 之量化60 5.3.3 MLC 3Read 之量化62 5.3.4 MLC 6Read 之量化63 5.3.5 MLC 7Read 之量化65 第六章 結論68 參考文獻(REFERENCES)69zh_TW
dc.language.isozh_TWen_US
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0811201222391600en_US
dc.subject多階層快閃記憶體zh_TW
dc.subjectMulti-Level Flash Memoriesen_US
dc.subject低密度奇偶查核碼zh_TW
dc.subjectLDPCen_US
dc.title應用於多階層快閃記憶體的低密度奇偶查核解碼器之最佳量化分析zh_TW
dc.titleOptimized Quantization Analysis for LDPC Decoders in Multi-Level Flash Memoriesen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1zh_TW-
item.grantfulltextnone-
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