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Circuit Design of Low Error-Floor LDPC Decoders Using R-LMSA with Post-Processing Technique for Wireless Systems
|關鍵字:||低密度同位元查核碼;LDPC;錯誤基數;後處理技巧;Error floor;post-processing||出版社:||電機工程學系所||引用:|| R. G. Gallager, “Low density parity check node codes,” IRE Trans. Inf. Theory, vol. IT-8, no.1, pp. 21-28, Jan. 1962.  IEEE draft standard for information technology-telecommunications and information wxchange between systems-local and metropolitan area networks-specific requirements-part 11: wireless LAN medium amendment: enhancements for higher throughput, Feb. 2007, IEEE Std. 802.11n.  IEEE standard for local and metropolitan area networks part 16: air interface for fixed and mobile broadband wireless access systems amendment 2: physical and medium access control layers for combined fixed and mobile operation in licensed bands and corrigendum 1, Feb. 2006, IEEE Std. 802. 16e.  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Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006.||摘要:||
本論文提出應用於無線傳輸系統之低錯誤基數R-LMSA LDPC解碼器與後處理技術之電路設計。本主題有幾個主要的重點 : (1).建構一個(3,15) -LDPC (480,2400)分割轉移矩陣(Partition and Shift LDPC, PS-LDPC)，其碼率為4/5，Girth為8。(2).提出改良後的Layered Min Sum Algorithm，在本論文中，將此演算法稱之為Reset Layer Min Sum Algorithm (R-LMSA)，解決LDPC解碼器因為量化而產生的錯誤基數現象，有效的降低錯誤基數(Error Floor)的發生。 (3).LDPC解碼器架構採用雙路徑部分平行式架構，在切管線使頻率上升的同時，亦不造成電路閒置的情形，使傳輸率倍增。(4).使用TSMC 90nm CMOS技術實作後，晶片核心面積為2.97mm2，最高工作頻率為188MHz。固定解碼次數7次下，Throughput為10.74 Gb/s，在電壓供應0.9伏特時，其功率消耗為287 mW。
其次，由於LDPC解碼器常發生之錯誤基數(Error Floor)現象，可分為量化錯誤(Quantization Error)及吸收錯誤(Absorbing Error)。本論文除了提出Reset Layer Min Sum Algorithm的演算法，在不用增加任何硬體面積下，解決LDPC解碼器因為量化錯誤(Quantization Error)所產生的錯誤基數現象，使得錯誤基數發生現象降至誤碼率(Bit Error Rate)為10-7以下，雖符合一般無線通訊的規格要求，但對於BER要求小於10-7系統中，只解決量化錯誤(Quantization Error)必然是不足的，因此本論文也針對吸收錯誤(Absorbing Error)所造成的錯誤基數現象進行研究與分析並提出一個後處理技巧，本論文稱之為Check Node Tracing with Boundary Search (CNTBS)。經過模擬分析證明LDPC解碼器在使用R-LMSA並搭配CNTBS技巧後，可以有效的降低錯誤基數的發生。
In this thesis, low error floor LDPC decoders using R-LMSA with a post-processing technique for wireless systems is presented with four major contributions. Firstly, a partition and shift LDPC (PS-LDPC) codes (480, 2400) is constructed with 4/5 coding rate and girth of 8. Secondly, an improved algorithm, named Reset Layer Min Sum Algorithm (R-LMSA), is proposed to lower the error floor of LDPC decoder due to quantization errors. The third is the proposed dual-path pipelined partial parallel architecture can increase the operating frequency, and double the throughput without idled circuit blocks. The last is the architecture was designed using the TSMC 90nm CMOS technology. The maximum frequency reaches 188MHz with the core area of 2.97mm2 at supply voltage of 0.9V. The throughput is 10.74Gbps for 7 iterations per decoding process with the power consumptions of 287mW.
There are two types of errors that result in the error floor in a LDPC decoder. One is owing to quantization errors, the other are absorbing errors. To solve the quantization errors, the proposed R-LMSA lowers the error floor less than BER = 10-7 without any hardware cost. Although it complys with the requirement of the most wireless systems, some other applications may need BER < 10-7. Therefor, we propose a new post processing technique, named Check Node Tracing with Boundary Search (CNTBS), to further reduce the error floor due to absorbing errors. After the analysis by simulations, the BER is effectively lower than 10-7 when R-LMSA is combined with the CNTBS technique.
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