Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9301
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dc.contributor林泓均zh_TW
dc.contributorHong-chin Linen_US
dc.contributor.author林學群zh_TW
dc.contributor.authorLin, Hsueh-Chunen_US
dc.contributor.other電機工程學系所zh_TW
dc.date2012en_US
dc.date.accessioned2014-06-06T06:43:02Z-
dc.date.available2014-06-06T06:43:02Z-
dc.identifierU0005-2607201213533000en_US
dc.identifier.citation[1] R. G. Gallager, “Low density parity check node codes,” IRE Trans. Inf. Theory, vol. IT-8, no.1, pp. 21-28, Jan. 1962. [2] IEEE draft standard for information technology-telecommunications and information wxchange between systems-local and metropolitan area networks-specific requirements-part 11: wireless LAN medium amendment: enhancements for higher throughput, Feb. 2007, IEEE Std. 802.11n. [3] IEEE standard for local and metropolitan area networks part 16: air interface for fixed and mobile broadband wireless access systems amendment 2: physical and medium access control layers for combined fixed and mobile operation in licensed bands and corrigendum 1, Feb. 2006, IEEE Std. 802. 16e. [4] IEEE standard for information technology-telecommunications and Information exchange between systems-local and metropolitan area networks-specific requirements-part 3: carrier sense multiple access with collision detection access method and physical layer specifications, Sep. 2006, IEEE Std. 802.3an. [5] D. J. C. MacKay and R. M. Neal, “Near Shannon limit performance of low density parity check codes,” Electron. Lett., vol. 32, no. 18, pp. 1645-1646, Aug. 1996. [6] N. Wiberg, “codes and decoding on general graphs,” Ph.D. thesis, Linkoping University, Sweden, 1996. [7] D. J. C. MacKay, “Gallager codes that are better than turbo codes,” in Proc. 36th Allerton Conf. Communications, Control, and Computing, Sept. 1998. [8] E. M. Kurtas, A. V. Kuznetsov, I. Djurdjevic, “System perspectives for the application of structured LDPC codes to data storage devices,” IEEE Trans. On Magnetics, vol. 42, no. 2, Feb. 2006. [9] L. Chen, J. Xu, I. Djurdjevic, and S. Lin, “Near Shannon limit quasi-cyclic low density parity check codes,” IEEE Trans. On Communications, vol. 52, no.7, July 2004. [10] J. Membe and J. M. F. Moura, “Partition-and-shift LDPC codes,” IEEE Transactions on Magnetics, vol. 41, no. 10, Oct. 2005. [11] X. Y. Shih, C. Z. Zhan, and A. Y. Wu, “A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications,” IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 301-304, Nov. 2008. [12] F. R. Kshischang and B. J. Frey, “Iterative decoding of compound codes by probability propagation in graphical models,” IEEE Journal on Selected Areas in Communications, vol. 16, pp. 219-230, Feb. 1998. [13] 王泓人, ”Design of Low Power Dual-Path PS-LDPC Decoder,” 碩士論文,中興大學,電機所,中華民國九十八年七月. [14] J. Hagenauer, E. Offer, L. Papke, “Iterative decoding of binary block and convolutional codes,” IEEE Trans. On Inform. Theory, vol. 42, no. 2, pp. 429-445, March 1996. [15] J. Zang, M. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., vol. 53, no. 2, pp. 209-213, Feb. 2005. [16] D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Proc. IEEE Workshop on SiPS., pp. 107-112, Oct. 2004. [17] K. Zhang, X. Huang, Z. Wang, “High-Throughput layered decoder implementation for quasi-cyclic LDPC codes,” IEEE JSAC, vol. 27, no. 6, Aug. 2009. [18] A. Blanksby and C. Howland, “A 690-mw 1-Gb/s 1024-b,rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404–412, Mar. 2002. [19] E. Yeo, B. Nikolic and V. Anantharam, “Architectures and implementations of Low density parity check decoding algorithms,” in Proc. Midwest Symposium on Circuits and Systems, vol. 3, pp. 437-440, Aug. 2002. [20] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006. [21] X. Y. Shih, C. Z. Zhan, and A. Y. Wu, “A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications,” IEEE Asian Solid-State Citcuits Conf. (ASSCC), pp. 301-304, Nov. 2008. [22] A. Darabiha, A. C. Carusone, and F. R. Kschischang, “Power reduction techn-iques for LDPC decoders,” IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 1835–1845, Aug. 2008. [23] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006. [24] C.-H. Liu, S.-W. Yen, C.-L. Chen, H.-C. Chang, C.-Y. Lee, Y.-S. Hsu, and S.-J. Jou, “An LDPC decoder chip based on self-routing network for IEEE 802.16e applications,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 684–694, Mar. 2008. [25] S. Allpress, C. Luschi, and S. Felix, “Exact and approximated expressions of the log-likelihood ratio for 16-QAM signals,” ACSSC ’04, vol. 1, pp. 794–798, Pacific Grove, Calif, USA, November 2004. [26] E. Yao, S.Yang, W. Jiang “A simplified soft decision demapping algorithm of 16-APSK signals in AWGN channels,” Networks Security Wireless Communications and Trusted Computing (NSWCTC), pp. 24-25, April 2010. [27] F. Tosato, P. Bisaglia, “Simplified soft-output demapper for binary interleaved COFDM with application to HIPERLAN/2,” International Communication Conference (ICC), April 2002. [28] Y. Miyata, K. Kubo, H. Yoshida, and T. Mizuochi, “Proposal for frame structure of optical channel transport unit employing LDPC codes for 100 Gb/s FEC,” Optical Fiber Communications, pp. 1-3, Mar. 2009. [29] Z. Zhang, L. Doleck, B.Nikolic, V. Anantharam, and M. Wainwright, “Lowering LDPC error floors by postprocessing,” Proc. IEEE on Clob. Tlelcom, Conf. Cannes, France, pp. 1-6, Dec. 2008. [30] Jingyu Kang, Qin Huang, Shu Lin, and Khaled Abdel-Ghaffar, “An iterative decoding algorithm with backtracking to lower the error-floors,” IEEE Transactions on Communications, vol. 59, pp. 64-73, 2011. [31] T. Richardson, “Error floors of LDPC codes,” in Proc. Allerton Conf. Commun., Control, Computing, Monticello, IL, pp. 1426-1435, Oct. 2003. [32] Z. Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic, “An efficient 10GBase-T Ethernet LDPC decoder design with low error floors,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 843–855, Apr. 2010. [33] D. MacKay and M. Postol, “Weaknesses of margulis and ramanujan-margulis lowdensity parity-check codes,” Electronic Notes in Theoretical Computer Science, vol. 74, 2003. [34] C.-C. Wang, S. R. Kulkarni, and H. V. Poor, “Finding all small error-prone substructures in LDPC codes,” IEEE Trans. Inf. Theory, vol. 55,no. 5, pp. 1976–1998, May 2009. [35] C. Di, D. Proietti, E. Telatar, T. Richardson, and R. Urbanke, “Finite length analysis of low-density parity-check codes,” IEEE Trans. Inf. Theory, vol. 48, no. 6, pp. 1570–1579, June 2002. [36] L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic,“Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes,” IEEE Trans. Inf. Theory, vol. 56, no. 1, pp. 181–201, Jan. 2010. [37] Haiyang Liu, Yan Li, Lianrong Ma, Jie Chen,“On the smallest absorbing sets of LDPC codes from finite planes,” IEEE Trans. Inf. Theory, vol. 58, no. 6, pp. 4014–4020, Jan. 2012. [38] C. Schlegel, Shuai Zhang,“On the dynamics of the error floor behavior in (regular) LDPC codes,” IEEE Trans. Inf. Theory, vol. 56, no. 7, pp. 3248–3264, Jan. 2010. [39] L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, “Investigation of error floors of structured low-density parity-check codes by hardware emulation,” IEEE GLOBECOM., pp. 1–6, 2006. [40] Jingyu Kang; Li Zhang; Zhi Ding; Shu Lin,“A two-stage iterative decoding of LDPC codes for lowering error floors,” IEEE GLOBECOM., pp. 1–4, 2008. [41] L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic,“Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices,” IEEE Trans. Comm., vol. 57, no. 11, pp. 3258–3268, 2009. [42] 姚長昆,”VLSI implementation of high throughput combined RS and LDPC decoders for optical communications,” 碩士論文,中興大學,電機所,中華民國九十九年七月. [43] K. Zhang, X. Huang, Z. Wang, “High-throughput layered decoder implementation for quasi-cyclic LDPC codes,” IEEE JSAC, vol. 27, no. 6, Aug. 2009. [44] C. Zhang, Z. Wang, J. Sha, Li Li, and J. Lin, “Flexible LDPC decoder design for multigigabit-per-second applications,” IEEE Tran. Circuits and System I, vol. 57, no. 1, Jan. 2010. [45] Kyung-Il Baek, Hanho Lee, Chang-Seok Choi, Sangmin Kim, G.E. Sobelman , “A high-throughput LDPC decoder architecture for high-rate WPAN systems,” IEEE International Symposium on Circuits and Systems, pp. 1311–1314, 2011. [46] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE J. Solid-State Circuits, vol. 41, pp. 684-698, Mar. 2006.en_US
dc.identifier.urihttp://hdl.handle.net/11455/9301-
dc.description.abstract本論文提出應用於無線傳輸系統之低錯誤基數R-LMSA LDPC解碼器與後處理技術之電路設計。本主題有幾個主要的重點 : (1).建構一個(3,15) -LDPC (480,2400)分割轉移矩陣(Partition and Shift LDPC, PS-LDPC),其碼率為4/5,Girth為8。(2).提出改良後的Layered Min Sum Algorithm,在本論文中,將此演算法稱之為Reset Layer Min Sum Algorithm (R-LMSA),解決LDPC解碼器因為量化而產生的錯誤基數現象,有效的降低錯誤基數(Error Floor)的發生。 (3).LDPC解碼器架構採用雙路徑部分平行式架構,在切管線使頻率上升的同時,亦不造成電路閒置的情形,使傳輸率倍增。(4).使用TSMC 90nm CMOS技術實作後,晶片核心面積為2.97mm2,最高工作頻率為188MHz。固定解碼次數7次下,Throughput為10.74 Gb/s,在電壓供應0.9伏特時,其功率消耗為287 mW。 其次,由於LDPC解碼器常發生之錯誤基數(Error Floor)現象,可分為量化錯誤(Quantization Error)及吸收錯誤(Absorbing Error)。本論文除了提出Reset Layer Min Sum Algorithm的演算法,在不用增加任何硬體面積下,解決LDPC解碼器因為量化錯誤(Quantization Error)所產生的錯誤基數現象,使得錯誤基數發生現象降至誤碼率(Bit Error Rate)為10-7以下,雖符合一般無線通訊的規格要求,但對於BER要求小於10-7系統中,只解決量化錯誤(Quantization Error)必然是不足的,因此本論文也針對吸收錯誤(Absorbing Error)所造成的錯誤基數現象進行研究與分析並提出一個後處理技巧,本論文稱之為Check Node Tracing with Boundary Search (CNTBS)。經過模擬分析證明LDPC解碼器在使用R-LMSA並搭配CNTBS技巧後,可以有效的降低錯誤基數的發生。zh_TW
dc.description.abstractIn this thesis, low error floor LDPC decoders using R-LMSA with a post-processing technique for wireless systems is presented with four major contributions. Firstly, a partition and shift LDPC (PS-LDPC) codes (480, 2400) is constructed with 4/5 coding rate and girth of 8. Secondly, an improved algorithm, named Reset Layer Min Sum Algorithm (R-LMSA), is proposed to lower the error floor of LDPC decoder due to quantization errors. The third is the proposed dual-path pipelined partial parallel architecture can increase the operating frequency, and double the throughput without idled circuit blocks. The last is the architecture was designed using the TSMC 90nm CMOS technology. The maximum frequency reaches 188MHz with the core area of 2.97mm2 at supply voltage of 0.9V. The throughput is 10.74Gbps for 7 iterations per decoding process with the power consumptions of 287mW. There are two types of errors that result in the error floor in a LDPC decoder. One is owing to quantization errors, the other are absorbing errors. To solve the quantization errors, the proposed R-LMSA lowers the error floor less than BER = 10-7 without any hardware cost. Although it complys with the requirement of the most wireless systems, some other applications may need BER < 10-7. Therefor, we propose a new post processing technique, named Check Node Tracing with Boundary Search (CNTBS), to further reduce the error floor due to absorbing errors. After the analysis by simulations, the BER is effectively lower than 10-7 when R-LMSA is combined with the CNTBS technique.en_US
dc.description.tableofcontents誌謝 i 中文摘要 ii ABSTRACT iii 目錄 iv 第一章 序論 1 1.1無線通訊系統及錯誤更正碼簡介 1 1.2研究動機 2 1.3 論文架構 4 第二章 低密度同位元查核碼之編碼與解碼 5 2.1 低密度同位查核碼基本概念 5 2.1.1 Tanner Graph 5 2.1.2 LDPC Code之定義 6 2.2 結構化低密度同位查核碼 7 2.2.1 QC-LDPC Code 7 2.2.2 分割轉移矩陣 PS-LDPC CODE 9 2.3 低密度同位查核碼之編碼 12 2.3.1產生矩陣法 12 2.3.2 下三角矩陣逼近法 13 2.4 低密度同位查核碼之解碼 15 2.4.1 Message Passing Algorithm 15 2.4.2 Sum-Product Algorithm 16 2.5 低密度同位查核碼解碼之演算法 20 2.5.1 Log Sum-Product Algorithm 20 2.5.2 Min-Sum Algorithm 21 2.5.3 Layered Min Sum Algorithm 22 2.6 低密度同位查核碼解碼架構介紹 24 2.6.1全平行式架構 25 2.6.2 序列式架構 25 2.6.3 部分平行式架構 26 第三章建構結構化低密度同位元查核矩陣及效能分析 27 3.1 分割轉移矩陣效能分析 28 3.2 LOG LIKELIHOOD RATIO 29 3.2.1 LLR背景介紹 30 3.3.2 LLR數值範圍分析 31 3.2.3 數值量化之觀念 33 3.3.4 數值量化擴充之概念 33 3.2.5 LDPC效能分析 35 第四章 低密度同位元查核碼之錯誤基數分析 38 4.1 相關研究 38 4.1.1 RS解碼器[28][41] 38 4.1.2 解碼後進行後處理(Post-Processing) 39 4.2降低錯誤基數的方法與研究 39 4.2.1相關名詞解釋 40 4.2.2 錯誤基數的分析 43 4.3降低錯誤基數的方法 47 4.3.1 Quantization Error 47 4.3.2 Absorbing Error 55 4.4 文獻比較 61 第五章 低錯誤基數之高傳輸率低密度同位元查核碼電路設計 62 5.1 R-LMSA LDPC 效能模擬 62 5.2 LDPC硬體架構 63 5.2.1 LDPC Decoder架構簡介 63 5.2.2 雙路徑解碼時序設計 64 5.2.3 Input Buffer 67 5.2.4 Router 67 5.2.5 LMSA Unit 68 5.2.6 R register 72 5.2.7 Lqj Shift Register 72 5.2.8 Hard Decision Buffer Unit 73 5.3硬體效能與文獻比較 74 5.3.1晶片設計流程與結果 74 5.3.2硬體效能與文獻比較 76 第六章 結論 78 參考文獻(REFERENCES) 79zh_TW
dc.language.isozh_TWen_US
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2607201213533000en_US
dc.subject低密度同位元查核碼zh_TW
dc.subjectLDPCen_US
dc.subject錯誤基數zh_TW
dc.subject後處理技巧zh_TW
dc.subjectError flooren_US
dc.subjectpost-processingen_US
dc.title應用於無線傳輸系統之低錯誤基數R-LMSA LDPC解碼器與後處理技術之電路設計zh_TW
dc.titleCircuit Design of Low Error-Floor LDPC Decoders Using R-LMSA with Post-Processing Technique for Wireless Systemsen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1zh_TW-
item.grantfulltextnone-
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