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標題: 應用於防撞雷達系統之頻率合成器
A Frequency Synthesizer Implementation of Collision Avoidance Radar Systems
作者: 許祐豪
Hsu, Yu-Hao
關鍵字: 壓控振盪器;Voltage Controlled Oscillator;除頻器;電荷幫浦;相位頻率偵測器;迴路濾波器;Frqeuency Divider;Charge Pump;Phase Frequency Detector;Loop Filter
出版社: 電機工程學系所
引用: [1] Koukab, A. ,"LC-VCO Design With Dual-Gm, Boosted for RF Oscillation and Attenuated for LF Noise", IEEE Microwave and Wireless Components Letters, pp. 675-677, 2010 Dec. [2] C.-C. Li, T.-P. Wang, C.-C. Kuo, M.-C. Chuang, and H. Wang, "A 21 GHz complementary transformer coupled CMOS VCO", IEEE Microwave and Wireless Components Letters, pp. 278-280, 2008 April [3] R. Aparicio and A. Hajimiri, "A noise-shifting differential Colpitts VCO", IEEE Journal of Solid-State Circuits , pp. 1728-1736, 2000 Dec. [4] Tang-Nian Luo, and Chen, Y.-J.E., "A 0.8-mW 55-GHz Dual-Injection-Locked CMOS Frequency Divider", IEEE Transactions on Microwave Theory and Techniques , pp.620-625, 2008 March [5] S. Rong, A. W. L. Ng, and H. C. Luong, "0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13μm CMOS" ,IEEE International Solid-State Circuits Conference, pp. 96-97,2009 Feb. [6] Tang-Nian Luo,Shuen-Yin Bai,Yi-Jan Emery Chen, "A 60-GHz 0.13μm CMOS Divide-by-Three Frequency Divider" , IEEE Transactions on Microwave Theory and Techniques, pp. 2409-2415, 2008 Nov. [7] D. J. Young, S. J. Mallin, and M. Cross, "2GHz CMOS voltage-controlled oscillator with optimal design of phase noise and power dissipation" , IEEE Radio Frequency Integrated Circuits Symposium, pp. 131-134, 2007 Jun. [8] T. Song, S. Ko, D. Cho, H. Oh, C. Chung, and E. Yoon, "A 5GHz transformer-coupled CMOS VCO using bias-level shifting technique" , IEEE Radio Frequency Integrated Circuits Symposium, pp. 127-130, 2004 Jun. [9] Y. Wachi, T. Nagasaku, and H. Kondoh, "A 28 GHz low-phase-noise CMOSVCO using an amplitude-redistribution technique" ,IEEE International Solid-State Circuits Conference, pp. 482-483, 2008 Feb. [10] 王繼豪,"應用於頻率合成器之高性能子電路之研製",國立中興大學電機工程 學系碩士學位論文,2011 July [11] 傅冠霖,"LC-Tank振盪器相位雜訊與消耗功率設計之權衡與寬頻注入鎖定除頻器",國立中興大學電機工程學系碩士學位論文,2011 Jan [12] 劉深淵,楊清淵,"鎖相迴路",滄海書局,1998 [13] 吳哲偉,"設計應用於頻率合成器之低功率子電路",國立中興大學電機工程學 系碩士學位論文, 2011 July [14] Behzad Razavi, "RF Microelectronics ", Prentice Hall PTR, 2009 [15] D. B. Leeson, "A simple model of feedback oscillator noise spectrum" ,IEEE Proceedings, pp.180-181,1966 February [16] Application Note 1001,National Semiconductor Co., 2011 July [17] 陳信瑲,"具有高功率、超寬頻表現在W-頻段(75–110GHz)的光子傳輸器",國 立交通大學顯示科技研究所碩士學位論文, 2010 April [18] Lianming Li, Patrick Reynaert, and Michiel S. J. Steyaert, "Design and Analysis of a 90nm mm-Wave Oscillator Using Inductive-Division LC Tank" ,IEEE Journal of Solid-State Circuits, pp.1950-1958, 2009 July [19] D. B. Leeson, "A simple model of feedback oscillator noise spectrum" ,IEEE Proceedings , pp.180-181,1966 February [20] Chethan Rao, Alvin Wang, Shaishav Desai, "A 0.46ps RJrms 5GHz Wideband LC PLL for Multi-Protocol 10Gb/s SerDes" , IEEE Custom Integrated Circuits Conference , pp.13-16, 2009 Spet. [21] Stephen P. Bruss and Richard R. Spencer, "A 5GHz CMOS PLL with Low KVCO and Extended Fine-Tuning Range" ,IEEE Radio Frequency Integrated Circuits Symposium, pp. 669-672, 2008 April [22] J.-O. Plouchart, J. Kim, V. Karam et al., "Performance variation of a 66GHz static CML divider in a 90nm SOI CMOS" ,IEEE International Solid-State Circuits Conference, pp. 526-527, 2006 Feb. [23] Yuan Mo, Efstratios Skafidas, Rob Evans and Iven Mareels, "A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-μm CMOS Technology for High Speed Millimeter-Wave Wireless Systems" ,IEEE International Conference on Circuits and Systems for Communications, pp. 26-28, 2008 May [24] Chunyuan Zhou, Lei Zhang, "Injection-Locking-Based Power and Speed Optimization of CML Dividers" ,IEEE Transactions on Circuits and Systems, pp. 565-569, 2011 Sept. [25] Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, "Wideband mmWave CML Static Divider in 65nm SOI CMOS Technology" , IEEE Custom Integrated Circuits Conference, pp. 21-24, 2008 Sept. [26] Wei Deng, Kenichi Okada, and Akira Matsuzawa, " A 0.5-V, 0.05-to-3.2 GHz, 4.1-to-6.4 GHz LC-VCO using E-TSPC frequency divider with forward body bias for sub-picosecond-jitter clock generation" ,IEEE Asian Solid State Circuits Conference, pp. 8-10, 2010 Nov. [27] J. P. Carmo, P. M. Mendes, J. H. Correia, " A 4.2mW 5.7-GHz frequency synthesizer with dynamic-logic (TSPC) frequency divider" ,International Conference on Telecommunications, pp.25-27, 2009 May [28] Seungsoo Kim and Hyunchol Shin, "Investigation of Forward Body Bias Effects on TSPC RF Frequency Dividers in 0.18μm CMOS" ,International SoC Design Conference, pp. 24-25, 2008 Nov. [29] X. P. Yu, M. A. Do, J. G. Ma, K. S. Yeo, "A New Phase Noise Model for TSPC based divider" ,IFIP International Conference on Very Large Scale Integration, pp.16-18, 2006 Oct. [30] Rui-feng Liu. Yong-ming Li, Hong-vi Chen, "A Fully Symmetrical PFD for Fast Locking Low Jitter PLL" , 5th International Conference on ASIC, pp. 21-24, 2003 Oct. [31] Jun-Han Bae, Kyoung-Ho Kim, Seok Kim, Kee-Won Kwon, and Jung-Hoon, "A Low-Power Dual-PFD Phase-Rotating PLL with a PFD Controller for 5Gb/s Serial Links" ,IEEE International Symposium on Circuits and Systems, pp. 20-23, 2012 May [32] Yingmei, Chent; Zhigong, Wang; Li, Zhang, "A 5GHz 0.18-μm CMOS technology PLL with a symmetry PFD" ,International Conference on Microwave and Millimeter Wave Technology, pp.21-24, 2008 April [33] Yu-Jen Lai; Tsung-Hsien Lin; "A 10-GHz CMOS PLL with an Agile VCO Calibration" , Asian Solid-State Circuits Conference, pp.213-216, 2005 Nov. [34] Wei-Hao Chiu, Yu-Hsiang Huang, and Tsung-Hsien Lin, "A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-μm CMOS" ,Symposium on VLSI Circuits, pp. 16-18, 2009 June [35] C-Y. Kuo, J-Y. Chang and S-I. Liu, "A spur-reduction technique for a 5-GHz frequency synthesizer" ,IEEE Transactions on Circuits and Systems, pp. 526-533, 2006 March [36] 郭仁財 譯,"微波工程",高力圖書有限公司, 2010 [37] Harish Krishnaswamy, Hossein Hashemi, "A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable- siI-NAO-AO Phase Ring Oscillator and PLL Architecture" ,IEEE International Solid-State Circuits Conference, pp. 11-15, 2007 Feb. [38] Yifei Luo Kuan Zhou, "A 24GHz Multi-Phase PLL for Optical Communication" ,50th Midwest Symposium on Circuits and Systems, pp.5-8 2007 Aug. [39] Muhammad Kashif, Zahid Yaqoob Malik, Mubashar Yasin, Muhammad Imran Nawaz, "K-Band PLL Based Frequency Synthesizer" ,6th International Bhurban Conference on Applied Sciences and Technology, pp. 19-22, 2009 Jan. [40] Takashi Ohira, Haruhiko Kato, Katsuhiko Araki, Fuminori Ishitsuka, "A Compact Full MMIC Module for Ku-Band Phase-Locked Oscillators" ,IEEE Transactions on Microwave Theory and Techniques, pp. 723-728, 1989 Apr. [41] Yanping Ding and Kenneth K. , "A 21-GHz Fractional-N Synthesizer in 130-nm CMOS" , IEEE Symposium on VLSI Circuits, pp. 14-16, 2007 June [42] Tai-Cheng Lee and Yen-Chuang Huang, "The Design and Analysis of a Miller-Divider-Based Clock Generator for MBOA-UWB Application " ,IEEE Journal of Solid-State Circuits, pp. 16-18, 2006 June [43] Tai-Cheng Lee, Yen-Chuan Huang, "The Design and Analysis of a Miller-Divider-Based Clock Generator for MBOA-UWB Application" ,IEEE Journal of Solid-State Circuits, pp. 1253-1261, 2006 June [44] Wei-Sung Chang, Kai-Wen Tan, and Shawn S. H. Hsu, "A 56.5-72.2 GHz Transformer-Injection Miller Frequency Divider in 0.13-μm CMOS" ,IEEE Microwave and Wireless Components Letters, pp.393-395, 2010 July [45] Mohammed K. Ali, Viswanathan Subramanian, Tao Zhang, and Georg Boeck, "Design of Ka-band Miller Divider in 130 nm CMOS" ,IEEE International Symposium on Radio-Frequency Integration Technology, pp. 205-208, 2011 Dec. [46] 柯柏丞,”應用於雙頻帶系統之本地振盪訊號源電路設計,” 國立中興大學電機工程學系碩士學位論文,2010 July [47] Alan W.L. Ng, Gerry C.T. Leung, Ka-Chun Kwok, Lincoln L.K. Leung ,Howard C. Luong, "A 1V 24GHz 17.5mW PLL in 0.18μm CMOS" ,IEEE International Solid-State Circuits Conference, pp. 158-590, 2005 Feb. [48] Hao Shang, John W. M. Rogers and James Chiu, "A Fully Differential 24GHz Transmit PLL in a 0.13μm CMOS Technology" ,IEEE North-East Workshop on Circuits and Systems, pp.45-48, 2006 June [49] Olivier Mazouffre, Herve Lapuyade, Jean-Baptiste Begueret, Andreia Cathelin, Didier Belot, Patrick Hellmuth and Yann Deval, "A 23-24 GHz low power frequency synthesizer in 0.25μm SiGe" ,European Microwave Conference, pp.4-6, 2005 Oct. [50] Brian A. Floyd, "A 16−18.8-GHz sub-integer-N frequency synthesizer for 60-GHz transceivers" ,IEEE Journal of Solid-State Circuits, pp. 1076-1086, 2008 May [51] Yu-Shao Jerry Shiao, Guo-Wei Huang, Chia-Wei Chuang, Hsieh-Hung Hsieh, Chewn-Pu Jou and Fu-Lung Hsueh, "A 100-GHz Varactorless CMOS VCO Using Source Degeneration" , IEEE MTT-S International Microwave Symposium Digest, pp. 17-22, 2012 June [52] W. Volkaerts, M. Steyaert and P. Reynaert, "118GHz fundamental VCO with 7.8% tuning range in 65nm CMOS" ,IEEE Radio Frequency Integrated Circuits Symposium, pp.1-4, 2011 June [53] W. Badalawa, L. Seongwoong and M.Fujishima, "115GHz CMOS VCO with 4.4% tuning range" ,European Microwave Integrated Circuits Conference, pp. 28-29, 2009 Sept. [54] C. Cao and K. O, "A 140-GHz fundamental mode voltage controlled oscillator in 90-nm CMOS technology" , IEEE Microwave and Wireless Components Letters, pp. 555-557, 2006 Oct. [55] P.-C. Huang, R.-C. Liu, H.-Y. Chang, C.-S. Lin, M.-F. Lei, H. Wang, C.-Y. Su, C.-L. Chang, "A 131 GHz push-push VCO in 90-nm CMOS technology" ,IEEE Radio Frequency integrated Circuits Symposium, pp. 613-616, 2005 June [56] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, "A 114GHz VCO in 0.13 μm CMOS technology" , IEEE International Solid-State Circuits Conference, pp. 404-606, 2004 Feb.
文中的第一部份是以TSMC40nm製程實現一W band之壓控振盪器與注入鎖定頻率除頻器,此電路是因為頻率較高的關係而暫時先將RF的部份完成,經由量測確認電路可使用後再繼續將整個迴路完成,而量測到的可調範圍為10GHz,上下限從90.5GHz~100.5GHz,相位雜訊在1MHz的偏移量為-64dBc,由頻譜可知其輸出訊號頻率為壓控振盪器產生之頻率的一半,也就是有達到除二的效果,而壓控振盪器的訊號強度為-36dBm,注入鎖定除頻器的訊號強度為-28dBm,消耗功率為16.6mW。
最後要討論的部份是操作在汽車倒車雷達上的鎖相迴路,同樣是以TSMC0.18μm製程來實現,此系統在壓控振盪器的部份第一為電晶體並聯的方式來達到增加整體電路的轉導值的方法,使得電路較容易達到振盪條件,第二是源極退化電容架構,利用電晶體的寄生電容來降低整體電路的電容值,來達到較寬的可調範圍。頻率除頻器是將傳統米勒除頻器之共振腔以MOS電阻代替,使共振腔之Q值下降來達到增加鎖定範圍的效果,另外是在輸入端的NMOS加上PMOS以current bleeding來增加注入電流,而此改良也能達到增加鎖定範圍的效果。剩下之類比電路皆使用第二部分的5GHz鎖相迴路所建立的模型,而量測的部份在一開始因為晶片佈局時與接收端電路之LO端相接而有負載效應的影響導致量出來的結果與模擬不符,因而將兩電路短路的金屬層以雷射切割機切斷,再次量測即得到與模擬相近的結果,而可鎖定的範圍約2.2GHz,上下限從23.16GHz~25.37GHz,相位雜訊在1MHz的偏移量為-104dBc,輸出之訊號強度為-13.87dBm,消耗功率為21.72mW。
其他識別: U0005-0111201216500700
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