Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9332
標題: 應變矽基合金反轉層之載子遷移率研究
A Study of Carrier Mobility in the Strained Si-based Alloy Inversion Layer
作者: 謝秉峰
Hsieh, Ping-Feng
關鍵字: 應變;strain;遷移率;Split C-V量測;矽鍺;矽碳;mobility;Split C-V measurements;SiGe;SiC
出版社: 電機工程學系所
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摘要: 
使用新穎的矽基材料(如矽碳和矽鍺合金材質)製作金氧半場效電晶體,可達到成本低廉且製程完全相容的優勢。因此,本論文著重在使用新穎的矽基通道材料於MOSFETs的反轉層載子遷移率方面。首要的重點為矽基MOSFET反轉層中載子遷移率的能帶理論計算及實驗量測。我們在應變矽MOSFET元件中採用三種不同的通道材料:矽碳、矽鍺合金和鍺(較高極限的矽鍺合金與100%的鍺含量)做比較。接著,介紹矽碳合金的特性及應變矽碳通道NMOSFET元件。在PMOSFET元件方面,我們則研究應變矽鍺合金和純鍺兩種材料。同樣地,採用應變矽鍺和鍺通道於PMOSFETs。
探討前瞻應變矽金氧半場效電晶體於矽碳合金材料的特性且研究使用應變矽碳合金表面通道於NMOSFETs。採用超高真空化學氣相氣相沉積(UHVCVD)系統,以CH3SiH3作為矽和碳的成長氣源,在(110)矽基板上摻入少量的(~1%)碳含量成長伸張應變矽碳層。我們利用標準MOS製作過程於NOMSFTTs元件與降低熱預算是為了盡可能維持最小的應變鬆弛。我們在矽基板上的矽碳合金薄膜採用倒置空間圖分析應變的分佈。在室溫下,矽碳和矽標準元件的電子反轉層遷移率做比較。採用在伸張應變矽上成長鬆弛矽鍺層所製做的NMOSFETs,可觀察到電子遷移率的增加。在低溫下,矽碳元件的電子反轉層遷移率低於標準矽元件並顯現受到電荷所影響且也可能是隨機合金散射。
我們亦研究電洞遷移率於矽鍺合金反轉層。採用量子化k.p方法於矽鍺合金反轉層之中且使用Kubo-Greenwood公式計算電洞遷移率。藉由擬合量測低電場遷移率的矽和鍺來校正計算用到的模型參數。我們研究在(100)、(110)與(111)基板上之未受應變和雙軸應變矽鍺反轉層的合金極限遷移率。我們也闡述了矽與鍺於(100)、(110)與(111)PMOSFET之外機械單軸應力的影響。我們萃得矽和鍺的壓阻係數,施額外的機械單軸應力在(100)、(110)與(111)的PMOSFET於平行和垂直通道方向。
最後,我們研究成長於矽基板上之應變鍺通道的電洞遷移率。與研究鍺(110) PMOSFET於未應變與應變的次能帶結構及各種等效質量。我們以理論方式來研究PMOSFET於應變鍺(110)反轉層的等效質量與遷移率。計算上這裡考慮的應變條件主要成長於(110)矽基板上之鍺通道所引起的雙軸壓縮應變。此外,我們也考慮垂直等效電場所引起的量子侷限效應,進而擬合k.p方法所計算的次能帶結構的結果。我們計算在(110)矽基板上的應變鍺通道反轉層之電洞狀態密度等效質量(density of state effective mass, mc)、電導質量(conductivity mass, mσ)和量子化有效質量(quantization effective mass, mz)的影響。

MOSFETs formed from novel Si-based materials, such as silicon-carbon and silicon-germanium alloys, have the advantage of low cost and are simple to manufacture. Therefore, in this thesis we focus on carrier mobility in the inversion layer of MOSFETs using novel Si-based channel materials. The primary topic of this thesis is the theoretical calculation and experimental measurement of carrier mobility in a Si-based MOSFET inversion layer. We introduce three MOSFET channel materials: silicon-carbon, silicon-germanium alloy, and Ge (the upper limit of the silicon-germanium alloy with 100% germanium content), which show greater potential in comparison to strained Si MOSFET devices. We introduce strained silicon-carbon alloys and apply them to create a strained silicon-carbon channel NMOSFET. For PMOSFET devices, we introduce strained silicon-germanium alloys and Ge. Similarly, these two materials can be applied to create strained silicon-germanium and Ge channel PMOSFETs.
To investigate the characterization of silicon–carbon alloy materials for use in future strained Si MOSFETs, NMOSFETs using strained silicon–carbon alloy surface channels are reported in this work. Tensile-strained silicon-carbon layers with substitutional carbon content up to ~1% were epitaxially grown on (100) Si substrates by ultra-high vacuum chemical vapor deposition, using silane and methylsilane as the silicon and carbon sources, respectively. The NMOSFETs were fabricated using standard MOS processing with reduced thermal treatment in order to minimize the possibility of strain relaxation. A reciprocal space mapping method was used to analyze the strain distribution in the silicon–carbon alloy thin films on Si substrates. The election inversion layer mobilities of the Si1−xCx and Si control devices at room temperature are comparable. This is in contrast to the electron mobility enhancement observed in NMOSFETs fabricated using tensile-strained Si grown on relaxed SiGe layers. At low temperatures, the electron inversion layer mobility of Si1−xCx devices is lower than that of the Si controls, and appears to be affected by the charge, and possibly random alloy scattering.
We also study the hole mobility in the silicon-germanium alloy inversion layer. The hole mobility in the SiGe alloy inversion layer is calculated using the quantized k.p method and a Kubo-Greenwood mobility formula. The model parameters used in the calculations are calibrated by matching the measured low-field mobility of Si and Ge. We study alloy-limited mobility in the inversion layers of relaxed and biaxial strained SiGe on (100), (110) and (111) substrates. We also explore the impact of external mechanical uniaxial stress on the Si and Ge (100), (110), and (111) PMOSFET. We obtained piezoresistance coefficients of Si and Ge (100), (110), and (111) PMOSFETs with external mechanical uniaxial stress applied parallel and perpendicular to the channel direction.
Finally, we study the hole mobility in strained Ge layers grown on Si substrate. Sub-band structures and the effective mass of relaxed and strained Ge (110) PMOSFETs were investigated. The effective mass and mobility of the strained Ge (110) inversion layer in a PMOSFET are studied theoretically in this work. The strain condition considered in the calculations is the intrinsic strain resulting from growing the Ge layer on the (110) Si substrate. The quantum confinement effect resulting from the vertical effective electric field is incorporated into the k.p calculation. Various effective masses, such as the quantization effective mass, mz, density of states effective mass, mDOS, and conductivity mass, mC, as well as the hole mobility of a strained Ge (110) inversion layer for PMOS under substrate strain and various effective electric field strengths, are all investigated.
URI: http://hdl.handle.net/11455/9332
其他識別: U0005-2307201310542600
Appears in Collections:電機工程學系所

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