Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/9360
標題: 正交分頻多工通訊系統之快速傅立葉轉換與軟性輸出多輸入多輸出訊號偵測IP設計
FFT and Soft-output MIMO signal Detector IP designs for OFDM communication systems
作者: 陳怡佑
Chen, Yi-You
關鍵字: 實數快速傅立葉轉換;MIMO;軟性輸出多輸入多輸出訊號偵測;Soft-output;signal Detector;RFFT
出版社: 電機工程學系所
引用: 參考文獻 [1] K.W. Wong, C. Y. Tsui, R. S. K. Cheng, and W. H. Mow, “A VLSI Architecture of A K-best Lattice Decoding Algorithm for MIMO Channels,” IEEE International Symposium on Circuits and Systems, pp. III-273-III-276, May 2002. [2] E. Agrell, T. Eeicksson, A. Vardy, and K. Zeger,”Clost point search in lattics,”IEEE Treans. Inform. Theory, vol. 48, no. 8. pp. 2201-2214, Aug.2002. [3] J. Salz and S.B. Weinstein, “Fourier transform communication system,” ACM Conf. on Computers & Communication, Pine Mountain, GA, Oct. 1969. [4] A. Peled and A. Ruiz, “Frequency domain data transmission using reduced computational complexity algorithms,” in Proc. IEEE ICASSP, Denver, CO, 1980, pp. 964–967. [5] R. Lassalle and M. Alard, “Principles of modulation and channel coding for digital broadcasting for mobile receivers,” EBU Tech. Rev., no. 224, pp. 47–69, Aug. 1987. [6] IEEE Std. 802.11a, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5GHz Band” , 1999. [7] EWC HT PHY Specification, Enhanced Wireless Consortium publication, V1.27, 2005. [8] E. Bernard, J.G. Krammer, M. Sauer, and R. Schweizer, “A pipeline architecture for modified higher radix FFT,” Int. Conf. Acoust. Speech Signal Process., Mar. 1992, pp.617-620 [9] L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “A new VLSI-oriented FFT algorithm and implementation,” ASIC Conf., Sep. 1998, pp.337-341. [10] G. Jo Byung and H. Sunwoo Myung, “New Continuous-Flow Mixed-Radix (CFMR) FFT Processor Using Novel In-Place Strategy,” IEEE Trans. Circuits Syst. Regul. Pap., vol. 52, no. 5, pp. 911-919, May 2005. [11] Y.J. Moon and Y.I. Kim, “A mixed-radix 4-2 butterfly with simple bit reversing for ordering the output sequences,” Int. Conf. Adv. Commun. Technol., Feb. 2006, pp. 4-7. [12] H. Jiang, H. Luo, J. Tian, and W. Song, “Design of an Efficient FFT Processor for OFDM Systems,” IEEE Trans. Consum. Electron, vol. 51, no. 4, pp. 1099-1103, Nov. 2005. [13] E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, “A fast single-chip implementation of 8192 complex point FFT,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 300-305, Mar. 1995. [14] T. Sansaloni, A. Pe’rez-Pascual, V. Torres, J. Valls, “Efficient pipeline FFT processors for WLAN MIMO-OFDM systems,” Electron. Lett, vol. 41, no. 19, pp. 1043-1044, Sep. 2005. [15] Parhi, K.K. ; Grajal, J. “A Pipelined FFT Architecture for Real-Valued Signals,”Circuits and systems, vol.56,Issue 12,pp.2634-2643,Dec 2009. [16] G. J. Foschini, G. D. Golden, and R. A. Valenzuela, “V-Blast: An Architecture for Realizing Fery High Data rates Over the Rich-Scattering Wireless Channel,” Tech. Rep., 07733P. W. Wolniansky Holmdel, NJ: Bell Labs., Lucent Technol., Crawford Hill Lab., 1999. [17] B. M. Hochwald and S.T. Brink, “Achieving near-capacity on a multiple-antenna channel,”IEEE Trans.Commun., vol.51,no.3,pp.389-399,March 2003. [18] E.Viterbo andJ.Boutros,”A universal lattice code decoder for fading channels,”IEEE Trans.Inf.Theory,vol.45,no.5,pp.1639-1642,Jul.1999. [19] A.Burg,M.Borgmann,M.Wenk,M.Zellweger,W.Fichtner,and H.Bolcskei,”VLSI implementation of MIMO detection using the sphere decoding algorithm,”IEEE Fournal of Solid-State Circuits,vol 40,no.7,pp.1566-1577,July 2005. [20] C. Studer,A. Burg,H. Bolcskei,”Soft-output sphere decoding : algorithms and VLSI implementation,”IEEE Journal on Selected Areas in Communications,vol.26,no.2,pp.290-300,Feb.2008 [21] M.Wenk,M.Zellweger,A.Burg,N.Felber,andW.Fichter,”K-best MIMO detection VLSI architectures achieving up to 424 Mbps,”inProc.IEEE International Symposium on Circuits and Systems,pp.1151-1154,May 2006. [22] Z.Guo and P.Nilsson,”Alogorithm and implementation of the K-best sphere decoding for MIMO detection,”IEEE Journal on Selected Areas in Communications,vol.24,no.3,pp,491-503,mar.2006. [23] Sizhong Chen, Tong Zhang, and Yan Xin,”Relaxed K-best MIMO signal detector design and VLSI implementation,”IEEE Transaction on VLSI systems,vol.15,no.3,pp.328-337,March 2007. [24] K.Wong,C.Tsui,R.-K.Cheng,and W.Mow,”A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels,”in Proc.IEEE,vol.3,2002,pp.273-276. [25] A.D.Murugan,H.E.Gamal,M.O.Damen,andG.Caire,”A Unified Framework for Tree Search Decoding:Rediscovering the Seqential Decoder,”IEEE Trans.Inf.Theory,vol.52,no.3,pp.933-953,Mar.2006. [26] van Zelst, A.,van Nee, R.; Awater, G.A.;” Space division multiplexing (SDM) for OFDM systems,” in Vehicular Technology Conference Proceedings, Vol 2,15-18 May 2000 [27] Y.-T. Hwang and W.-D. Chen,” Design and Implementation of a High Throughput Fully-Parallel Complex-Valued QR Factorization Chip,” IET circuits, devices and systems, vol.5, no.5, pp. 424-432, Sept, 2011 [28] . R. van Nee, A. van Zelst and G. Awater,” Maximum likelihood decoding in a space division multiplexing system,” in Vehicular Technology Conference Proceedings, May 2000,pp.15-18 [29] Tsung-Hsueg Lee,”Design and implementation of a new complex sphere decoder for MIMO detection,”thesis,National Taiwan University,Taipei,Taiwan,2006. [30] To-PingWang,”Design of a new complex sphere decoder for soft-output MIMO detector,”M.S.thesis, National Taiwan University,Taipei,Taiwan,2007. [31] S.Yazdi,T.Kwasniewski,”Confgurable K-best MIMO Detector Architecture,”in Proc.ISCCSP,2008,pp.1565-1569. [32] C.-J. .Huang,C.-W. Yu,and H.-P. Ma,”A power-efficient configurable low-complexity MIMO detector,”IEEE Trand.Circuit and Syst.-I:Regular Papers,vol.56 ,no.2,pp.485-496,Feb.2009. [33] C.-H. Liao, T.-D. Chiueh,”A 74.8Mw soft-output detector IC for 8×8 spatial-multiplexing MIMO communications,”IEEE J. Solid-State Circuit, vol. 45,no.2,pp. 411-421.,2010 [34] N. Moezzi-Madani, T. Thorolfsson, and W. Davis,”A low-area flexible MIMO detector for Wifi/Wimax standards,”in DATE’10:Proceedings of the 2010 Design,Automation and Test Conference,mar.2010,pp.1633-1636 [35] S. Chen and T. Zhang, “Low power soft-output signal detector design for wireless MIMO communication system,” in Proc. International Symp. On Low Power Electronics and Dwsign,pp.232-237,2007
摘要: 
本論文應用正交分頻多工於光纖到家通訊與多輸入多輸出通訊系統上,在光纖通訊系統下設計出高速64點實數快速傅立葉轉換電路,利用演算法中的共軛特性來降低運算複雜度,並且將每階層中原先為複數運算變為實數運算來降低運算複雜度,同時也使每階層有相同的傳輸量(throughput),此系統規格所定義的實數快速傅立葉轉換取樣頻率為2GHz,本論文設計8路平行的硬體架構,使硬體工作頻率運作於250MHz;在多輸入多輸出4x4 64-QAM系統下設計軟性解調輸出,利用K最佳演算法中搜尋過程的每階層的最小誤差值與各位元最大PED值作為資訊,設計出四種軟性輸出演算法,分別為單次LLR值(One Pass LLR, OP)、漸進式更新LLR值(Progressive update LLR, PU)、最後階層更新LLR值-1(Final stage updata LLR-1, FSU1)與最後階層更新LLR值-2(Final stage updata LLR-2, FSU2四種;為了降低排序電路的負擔與運算節點,本論文設計出結合式列舉法(Combinative Enumeration);本論文設計改良平行氣泡排序(Simplify of Parallel Bubble-Slice Sort)電路將可以有效的加快排序速度,也降低比較器的使用;在所有運算過程中,將有使用乘法器電路都由移位乘法器(Shift Multiplier)所取而代之來降低硬體。
於模擬結果中發現實數快速傅立葉轉換演算法架構在錯誤率為10-3情況下,再大幅降低傳統的快速傅立葉轉換演算法運算量下僅僅只降低了0.4dB,將此模組實現在配有高速串型鏈路RocketIO的Xilinx的Virtex 5 LTX平台驗證上,工作頻率為251.3MHz,有效的取樣頻率可達到2.01GHz。運用K最佳演算法於軟性解碼輸出架構在K為8情況下,並且邊界值設定為±32,將此模組實現在Xilinx的Virtex 5 L5330平台驗證上,工作頻率為120MHz,吞吐量可達到720Mbps。

This thesis deals with the application of Orthogonal Frequency Division Multiplexing (OFDM) scheme in the optic fiber-to-the-home communications and Multi-input Multi-output (MIMO) communication systems. We first investigate on the design of a real-valued Fast Fourier Transform (RFFT) with high-speed 64 points in the fiber-optic communication system. The conjugate characteristic of the algorithm is utilized to reduce the computing complexity. Changing the complex-valued operation into real-valued in each stage can not only reduce the operational complexity but also make each stage operating on the same throughput. The sample frequency of RFFT is 2GHz to comply with the sampling rate. In this thesis, the design is eight-way parallel and the system working frequency are set the 250MHz.
We next investigation on the design of a soft-output detector in the 4x4 64-QAM MIMO system. The Search Process in the K-best algorithm is employed to seek through every stage for the minimum error and the maximum PED of each bit as the information. A total of four types of soft-output algorithm, i.e. , One Pass LLR, Progressive update LLR, Final stage updata LLR-1, and the Final stage updata LLR-2 are developed. A Combinative Enumeration scheme is adopted in this thesis to reduce the loading of sort circuit and node computation. To further enhance the efficiency of sorting scheme and to lower the utility rate of Comparator, a Simplified Parallel Bubble-Slice Sorter was designed. Simply, Shift Multipliers are used to replace the Conventional Multiplier for lower hardware complexity.
From the simulation results, we find that when the Bit Error Rate (BER) is significantly around 10-3, the real-valued Fast Fourier Transform can reduce the computing complexity. While the performance loss only 0.4dB when compared with conventional real-valued FFT design. To proposed FFT designs are realized using Xilinx''s Virtex 5 LTX validation platform with high speed RocketIO links. The implementation results show that the design can operate ate 251.3MHz and the effective sample frequency can reach 2.01GHz.For sort-output MIMO detector design, the application of K-best algorithm with K=8 and boundary=�32. The implementation results show that the design can operate ate 120MHz and the throughput can reach 720Mbps.
URI: http://hdl.handle.net/11455/9360
其他識別: U0005-2011201219082100
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.