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dc.contributorYin-Tsung Hwangen_US
dc.contributor.authorChen, Yi-Youen_US
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dc.description.abstract本論文應用正交分頻多工於光纖到家通訊與多輸入多輸出通訊系統上,在光纖通訊系統下設計出高速64點實數快速傅立葉轉換電路,利用演算法中的共軛特性來降低運算複雜度,並且將每階層中原先為複數運算變為實數運算來降低運算複雜度,同時也使每階層有相同的傳輸量(throughput),此系統規格所定義的實數快速傅立葉轉換取樣頻率為2GHz,本論文設計8路平行的硬體架構,使硬體工作頻率運作於250MHz;在多輸入多輸出4x4 64-QAM系統下設計軟性解調輸出,利用K最佳演算法中搜尋過程的每階層的最小誤差值與各位元最大PED值作為資訊,設計出四種軟性輸出演算法,分別為單次LLR值(One Pass LLR, OP)、漸進式更新LLR值(Progressive update LLR, PU)、最後階層更新LLR值-1(Final stage updata LLR-1, FSU1)與最後階層更新LLR值-2(Final stage updata LLR-2, FSU2四種;為了降低排序電路的負擔與運算節點,本論文設計出結合式列舉法(Combinative Enumeration);本論文設計改良平行氣泡排序(Simplify of Parallel Bubble-Slice Sort)電路將可以有效的加快排序速度,也降低比較器的使用;在所有運算過程中,將有使用乘法器電路都由移位乘法器(Shift Multiplier)所取而代之來降低硬體。 於模擬結果中發現實數快速傅立葉轉換演算法架構在錯誤率為10-3情況下,再大幅降低傳統的快速傅立葉轉換演算法運算量下僅僅只降低了0.4dB,將此模組實現在配有高速串型鏈路RocketIO的Xilinx的Virtex 5 LTX平台驗證上,工作頻率為251.3MHz,有效的取樣頻率可達到2.01GHz。運用K最佳演算法於軟性解碼輸出架構在K為8情況下,並且邊界值設定為±32,將此模組實現在Xilinx的Virtex 5 L5330平台驗證上,工作頻率為120MHz,吞吐量可達到720Mbps。zh_TW
dc.description.abstractThis thesis deals with the application of Orthogonal Frequency Division Multiplexing (OFDM) scheme in the optic fiber-to-the-home communications and Multi-input Multi-output (MIMO) communication systems. We first investigate on the design of a real-valued Fast Fourier Transform (RFFT) with high-speed 64 points in the fiber-optic communication system. The conjugate characteristic of the algorithm is utilized to reduce the computing complexity. Changing the complex-valued operation into real-valued in each stage can not only reduce the operational complexity but also make each stage operating on the same throughput. The sample frequency of RFFT is 2GHz to comply with the sampling rate. In this thesis, the design is eight-way parallel and the system working frequency are set the 250MHz. We next investigation on the design of a soft-output detector in the 4x4 64-QAM MIMO system. The Search Process in the K-best algorithm is employed to seek through every stage for the minimum error and the maximum PED of each bit as the information. A total of four types of soft-output algorithm, i.e. , One Pass LLR, Progressive update LLR, Final stage updata LLR-1, and the Final stage updata LLR-2 are developed. A Combinative Enumeration scheme is adopted in this thesis to reduce the loading of sort circuit and node computation. To further enhance the efficiency of sorting scheme and to lower the utility rate of Comparator, a Simplified Parallel Bubble-Slice Sorter was designed. Simply, Shift Multipliers are used to replace the Conventional Multiplier for lower hardware complexity. From the simulation results, we find that when the Bit Error Rate (BER) is significantly around 10-3, the real-valued Fast Fourier Transform can reduce the computing complexity. While the performance loss only 0.4dB when compared with conventional real-valued FFT design. To proposed FFT designs are realized using Xilinx''s Virtex 5 LTX validation platform with high speed RocketIO links. The implementation results show that the design can operate ate 251.3MHz and the effective sample frequency can reach 2.01GHz.For sort-output MIMO detector design, the application of K-best algorithm with K=8 and boundary=�32. The implementation results show that the design can operate ate 120MHz and the throughput can reach 720Mbps.en_US
dc.description.tableofcontents目錄 摘要 i Abstract ii 目錄 iii 表目錄 vi 圖目錄 ...vii 第一章 緒論 ..1 1.1 研究背景 ..1 1.2 研究動機 ..2 1.3 論文架構 ..3 第二章 正交分頻多工與多輸入多輸出系統介紹 ..4 2.1 正交分頻多工 ..4 2.1.1 正交分頻多工技術 ..5 2.1.2 正交分頻多工系統架構 ..7 2.1.3 保護區間和循環字首 ..8 2.2 多輸入多輸出系統 ..9 2.2.1 系統簡介 ..9 2.2.2 IEEE 802.11n 系統架構 11 2.2.3 MIMO-OFDM傳送端與接收端架構 12 2.2.4 信號模型 13 第三章 實數快速傅立葉設計與實現 14 3.1 系統規格 14 3.2 快速傅立葉演算法與架構 15 3.3 實數快速傅立葉轉換電路演算法 17 3.4 預先排序電路設計 23 3.5 實數快速傅立葉轉換硬體模組設計 25 3.6 實數快速傅立葉轉換字元長度模擬 32 3.7 FPGA實現結果 34 第四章 多輸入多輸出信號解碼介紹 35 4.1 多輸入多輸出信號解碼 35 4.1.1 線性解碼 35 4.1.2 非線性解碼 36 4.2 樹狀搜尋演算法 38 4.2.1 深度優先演算法 39 4.2.2 廣度優先演算法 40 4.2.3 最佳優先演算法 41 4.3 解碼輸出種類 42 4.3.1 硬性解調輸出 42 4.3.2 軟性解調輸出 42 4.4 演算法分析比較 44 第五章 K-Best軟性輸出設計 45 5.1 星座點列舉法 45 5.1.1 直接SE列舉法 46 5.1.2 表列舉法 47 5.1.3 實數列舉法 48 5.1.4 編碼式列舉法 49 5.1.5 結合式列舉法 50 5.2 排序演算法介紹 51 5.2.1 氣泡排序法 51 5.2.2 奇偶換位排序法 51 5.2.3 貝基排序法 52 5.2.4 平行氣泡排序法 53 5.2.5 改良平行氣泡排序法 54 5.2.6 列舉後排序法 55 5.3 軟性輸出 56 5.3.1 單次LLR值 57 5.3.2 漸進式更新LLR值 58 5.3.3 最後階層更新LLR值-1 59 5.3.4最後階層更新LLR值-2 60 5.4 演算法效能比較 61 第六章 硬體架構設計與實現 68 6.1 系統規格 68 6.2 軟性輸出硬體模組設計 68 6.3 各模組介紹 70 6.3.1 天線間干擾消除 70 6.3.2 結合式列舉法 71 6.3.3 各階層誤差值與歐基理德距離 72 6.3.4 位元初始值與最小誤差值 72 6.3.5 排序電路 73 6.3.6 當階層訊號選取與先前所有階層訊號選取 74 6.3.7 更新計算LLR值資訊 74 6.4 硬體設計與實現 75 6.5 FPFA實現結果 83 6.6 硬體效能比較 85 第七章 結論 86 參考文獻 88zh_TW
dc.subjectsignal Detectoren_US
dc.titleFFT and Soft-output MIMO signal Detector IP designs for OFDM communication systemsen_US
dc.typeThesis and Dissertationzh_TW
item.openairetypeThesis and Dissertation-
item.fulltextno fulltext-
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