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標題: 超音波影像之三維低複雜度最小變異無失真響應波束成形器設計
Three-dimensional Low Complexity Minmum Variance Distortionless Response Beamformer for Ultrasound Imaging
作者: 陳致穎
Zhi-Ying Chen
關鍵字: 最小變異無失真響應;波束成形器;超音波影像;Minmum Variance Distortionless Response;Beamformer;Ultrasound Imaging
引用: [1] Savord, Bernard, and Rod Solomon. 'Fully sampled matrix transducer for real time 3D ultrasonic imaging.' Ultrasonics, 2003 IEEE Symposium on. Vol. 1. IEEE, 2003, pp. 945–953. [2] L. C. Godara, 'Application of antenna arrays to mobile communications. II. Beam-forming and direction-of-arrival considerations,' Proceedings of the IEEE, vol. 85, pp. 1195-1245, 1997. [3] Sampson, Richard, et al. 'Sonic millip3de: A massively parallel 3d-stacked accelerator for 3d ultrasound.' High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on. IEEE, 2013, pp. 318–329. [4] Hager, Pascal Alexander, et al. 'Assessing the area/power/performance tradeoffs for an integrated fully-digital, large-scale 3D-ultrasound beamformer.' Biomedical Circuits and Systems Conference (BioCAS), 2014 IEEE. IEEE, 2014, pp. 228–231. [5] J. Durbin, 'The filtering of time series models,' Review of International Statistics Institute, vol. 28, pp. 223-244, 1960. [6] K. Sun-Yuan and H. Yu Hen, 'A highly concurrent algorithm and pipeleined architecture for solving Toeplitz systems,' Acoustics, Speech and Signal Processing, IEEE Transactions on, vol. 31, pp. 66-76, 1983. [7] Jiaxiang Xu, Jianhua Zhang, 'An Attempt to 3D Capon Beamforming,' 8th International Conference on Communications and Networking in China, 978-1-4799-1406-7, pp. 734-739, 2013 [8] Sampson, Richard, et al. 'Sonic millip3de: A massively parallel 3d-stacked accelerator for 3d ultrasound.' High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on. IEEE, 2013, pp. 318–329. [9] J. E. Volder, 'The CORDIC Trigonometric Computing Technique,' Electronic Computers, IRE Transactions on, vol. EC-8, pp. 330-334, 1959. [10] L. Jian, P. Stoica, and W. Zhisong, 'On robust Capon beamforming and diagonal loading,' Signal Processing, IEEE Transactions on, vol. 51, pp. 1702-1715, 2003. [11] P. A. Hager, Andrea Bartolini, and Luca Benini, 'Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second,' IEEE Trans. on VLSI Systems, vol. 24, no. 5, pp. 1936-1949, May. 2016 [12] 王信翔 '應用於二維/三維超聲波影像之高效率最小變異無失真響應波束成形器設計,' 國立中興大學電機工程學系研究所碩士論文, 2016年. [13] 洪柏源 '基於延遲總合與平形波束成形技術之高幀率三維超聲波影像系統, '國立中興大學電機工程學系研究所碩士論文, 2017年. [14] F. Vignon and M. R. Burcher, 'Capon beamforming in medical ultrasound imaging with focused beams,' IEEE Trans. Ultrason., Ferroelectr., Freq. Control, vol. 55, pp. 619-628, 2008. [15] J. Y. Lu, H. Zou, and J. F. Greenleaf, 'Biomedical ultrasound beam forming,'Ultrasound Med. Biol., vol. 20, pp. 403-28, 1994.
隨著科技的進步,對於醫療影像的需求,超音波影像被廣泛的應用,其系統具有低成本、即時性高的特性,影像成像的方式是利用超聲波發射出後反射接收訊號,根據訊號強度,組成體內組織影像。而此系統最重要的關鍵技術在於波束成形器(Beamformer)的設計,波束成形器相當於ㄧ個空間濾波器,利用空間資訊進行訊號品質提升使干擾訊號壓抑或消除,有良好的波束成形前處理,才能有清晰的影像解析。傳統延遲和加總(Delay-and-Sum, DAS)技術得到的超音波成像影像效果並不是非常理想,因此自適應性波束成形技術是較佳的選擇,但是三維影像相對於傳統二維影像,由於影像資料處理量龐大,需要耗費大量的記憶體,如何解決高維度的權重計算和傳統的影像取樣和平行波束成形(Parallel beamforming)影像取像也是一大問題。
本論文提出即時運算的三維的低複雜度最小變異無失真響應(Minimum Variance Distortionless Response, MVDR)之波束成形器電路設計。首先利用硬體即時的延遲計算,使的訊號到二維感測器陣列相位對齊,再利用少量的記憶體48k將一層Focal Point的資訊存取起來,進行三維MVDR權重的計算。
三維MVDR權重則是拆解成兩次的二維Beamforming計算,再將兩組二維的Beamforming權重組成三維的Beamforming 權重。而二維的MVDR權重,赫米遜自相關矩陣部份利用超音波訊號掃描速度高於人體組織變化的速度,因此其訊號具有Stationary特性以特普立茲矩陣(Toeplitz Matrix)來近似並以邱列斯基分解(Cholesky Decomposition)的運算方式來取代直接的反矩陣運算。由於特普立茲矩陣的特性,這邊可以利用舒爾分解(Schur Decomposition)來獲得邱列斯基分解的結果,將運算複雜度由O(N3)降低為O(N2) 。
在硬體設計階段,使用線性心縮矩陣(Linear Systolic Array)之設計架構,,並成功解決邱列斯基分解Forward及Backward Substitution所造成的Pipeline Bubble。加入許多電路設計與晶片實作技巧來達到高工作頻率及低運算複雜度的硬體設計。本設計最後以FPGA來實現。其中FPGA是使用Xilinx Vertex XC7z045ffg900的發展平台,並結合後處理模組來做成像驗證。根據FPGA implementation report,該設計可工作在124.754MHz,並達到超過每秒八十次的掃描速率。

Ultrasonic imaging has been widely used in various applications such as medical imaging. Compared with other medical imaging systems, ultrasonic imaging system has the characteristics of low cost and high availability. It trasmits ultrasonic waves to the human tissue and receives the reflected signals to construct the image. The most important key technology of this system is the beamformer design. The beamformer behaves like a spatial filter. It allows signal from a specific direction to pass and suppresses the remaining. This technique can improve the desired signal quality and reduce the interference signal. Conventional delay-and-sum (DAS) beamforming scheme is simple, non-adaptive but cannot always yield satisfactory result. Therefore, adaptive beamforming scheme, which adjust the beamforming dynamically subject to the received signals, is a better choice. Adaptive beamforming, however, requires massive computations. The computing complexity is even higher when 3D medical imaging is performed.
In view of this technical problem, this paper proposes a three-dimensional low-complexity adaptive beamforming scheme, Minimal Variance Distortion Response (MVDR) beamformer, and develops an efficient circuit design for real-time operations. A delay alignment module is first employed to synchronize the phases of signal received beamby the transducer array. A 3D MVDR beamforming is performed next and calculate the focal points from the nearest nappe to the farest one. The weights required in 3D MVDR beamforming are computed through two 2D beamforming processes. The two weighting vectors obtained are then cross-product to obtain the weighting matrix needed in 3D beamforming. In particular, 2D MVDR beamforming scheme is optimized to reduce the computing complexity significantly. Firstly, the auto-correlation matrix is approximated using a Toeplitz matrix, which makes the room for fast computing of its inverse matrix. To compute the inverse of a Toeplitz structured auto-correlation matrix, a combination of Cholesky and Schur decompositions is applied and the resultant computing complexity can be reduced from O(N3) to O(N2).
After the algorithm refinement, in the hardware design phase, linear systolic array is chosen as the basic computing architecture. Pipeline bubbles caused by the forward and backward substitutions after decomposition are also solved by using two asuucessive matrix vector multiplications. In the circuit domain, low complexity Coordinate Rotation Digital Computer (CORDIC) computing scheme is adopted to implement the complex divider operation. Various circuit optimization are also applied to achieve high operating frequency and low circuit complexity. The final design is implemented in a rapid prototyping platform equipped with a Xilinx Vertex XC7z045ffg900 FPGA device. The implementation result show that the hardware accelerator design can operate at 124.754 MHz and achieve a scan rate of more than 80 frames per second.
Rights: 同意授權瀏覽/列印電子全文服務,2021-08-31起公開。
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