Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/98393
標題: 扇出晶圓級封裝模壓參數最佳化之探討
Optimization of Fan-Out Wafer Level Package molding parameters
作者: 陳宥辰
Yu-Chen Chen
關鍵字: FOWLP;Warpage;封裝;熱應力;有限元素法;田口法分析;FOWLP;Warpage;Packaging;Thermal stress;Finite element method;Taguchi method
引用: [1] 矽品精密工業股份有限公司http://www.spil.com.tw/ [2] 日月光半導體製造股份有限公司http://ase.aseglobal.com/ [3] 元大投顧https://research.yuanta.com/login.html [4] S. S. Deng, S. J. Hwang, H. H. Lee, 'Warpage Prediction and Experiments of Fan-Out Wafer level Package During Encapsulation Process', IEEE Transactions on Components, Packaging and Manufacturing Technology, VOL. 3, NO. 3, MARCH 2013. [5] Y. S. Chang, S. J. Hwang, H. H. Lee, 'Study of P-V-T-C relation of EMC', J. Electron. Packag., vol. 124, no. 4, pp. 371-373, Dec. 2002. [6] S. J. Hwang, Y. S. Chang, 'Isobaric cure shrinkage behaviors of epoxy molding compound in isothermal state', J. Polymer Sci. Part B Polymer Phys., vol. 43, no. 17, pp. 2392-2398, Sep. 2005. [7] S. J. Hwang, Y. S. Chang, 'P-V-T-C equation for epoxy molding compound', IEEE Trans. Compon. Packag. Technol., vol. 29, no. 1, pp. 112-117, Mar. 2006. [8] C.-Y. Ho, Research on volume shrinkage behavior of liquid compound, Dept Eng. Sci., Nat. Cheng Kung Univ., 2009. [9] 李輝煌,田口方法-品質設計的原理與實務,ISBN:9789864126668,2012年出版。 [10] F. Hou, T. Lin, L. Cao, F. Liu, J. Li, X. Fan, G. Q. Zhang, 'Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan- Out Packag', IEEE TRANSACTIONS ON COMPONENTS, AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 10,OCTOBER 2017. [11] D.S. Huang, W.B. Tu, X.M Zhang, L.T. Tsai, T.Y. Wu, M.T. Lin, 'Using Taguchi method to obtain the optimal design of heat dissipation Reliability', 2016. DOI: 10.1016/j.microrel.2016.07.006. [12] ANSYS結構分析技術認證學程,工業技術研究院,經濟部工業局 機械產業培訓計畫,2012。 [13] 北京兆迪科技有限公司,ANSYS Worbench 14.0 結構分析快速入門進階與精通,電子工業出版社。 [14] Farrugia R, Grech I, Casha O, Gatt E, Micallef J, Ellul I, Duca R, Borg I, 'The analysis of warpage in wafer-level compression molding', Microsyst Technol (2017) 23:4025-4034 DOI 10.1007/s00542-015-2773-3. [15] Y. T. Lin, W.H Lai, C.L. Kao, J.W. Lou, P.F. Yang, C.Y. Wang, and C.A. Hseih, 'Wafer Warpage Experiments and Simulation for Fan-out Chip on Substrate', 2016 IEEE 66th Electronic Components and Technology Conference. [16] T. Braun, K.-F. Becker, S. Raatz, V. Bader, J. Bauer, R. Aschenbrenner, 'From Fan-out Wafer to Fan-out Panel Level Packaging', 2015 European Conference on Circuit Theory and Design (ECCTD). [17] R. Pemdse and J. Demmin, 'Test Structure and Finite Element Models for Chip Stress and Plastic Package Reliability', Proc. IEEE 1990 Int. Conference on Microelectronic Test Structure ,vol. 3, March 1990, pp.155-160. [18] H. C. Cheng, K. N. Chiang and C. K. Chen, 'Solder joint Reliability of Thermally Enhanced BGA Using a Finite-Volume-Weighted Averaging Technique', 第十六屆機械工程研討會論文集, 88年12月, p.370-377. [19] L. L. Mercado, H. Wieser, T. Hauck, 'Mold Delamination and Die Fracture Analysis of Mechatronic Packages', IEEE Electronic Component and Technology Conference, pp. 229-233, 2001. [20] Atila Mertol, 'Application of the Taguchi Method to Chip Scale Package(CSP) Design', IEEE, 23, pp.266-276, May 2000.
摘要: 
由於高接腳數的手機晶片或應用處理器需求,近期轉向採用扇出晶圓級封裝技術的發展趨勢。而從低成本化的觀點出發,扇出晶圓級封裝技術最顯著的優勢,就是可以省去載板,且封裝厚度也更加輕薄,有助於提升晶片商產品競爭力。但現今能有許多難題,諸如重新配線所產生的熱應力、封裝過程中因環氧樹酯材料與晶圓的熱膨脹係數不匹配,導致的翹曲,這些都是目前面臨的一大挑戰。
而本文主要研究目的則是著重在封裝模壓製程。並以四種控制因子分別為加工溫度、冷卻時間、環境溫度以及熱膨脹係數進行模擬,再搭配L9直交表快速找出最佳參數組合,之後在各別針對四種不同因子做延伸,最後發現越高的加工溫度所需冷卻制環境室溫時間成正比,而在相同條件下,越低的環境溫度可有望減少封裝體翹曲的程度。因此藉由各項參數因子對於翹曲的影響程度,以提供後續作業者一個參考依據。

The recent fan-out wafer level packaging has become the current trend. From the point of view of low cost, the most significant advantage of FOWLP is that it can save the carrier board and the thickness of the package is also thinner, which helps to enhance the competitiveness of the chip manufacturer. But today there are many challenges, such as warpage caused by the mismatch between the thermal expansion coefficients of EMC materials and wafers in the packaging process, which are currently facing a major challenge.
The main purpose of this paper is to focus on the package molding process. Four kinds of control factors are used to simulate the processing temperature, cooling time, ambient temperature and thermal expansion coefficient, and then the L9 orthogonal table is used to quickly find the best parameter combination, and then extend to each of the four different factors, and finally find the more The high processing temperature is proportional to the room temperature time required for the cooling environment, and under the same conditions, the lower the ambient temperature is expected to reduce the degree of warpage of the package. Therefore, the degree of influence of various parameter factors on warpage is provided to provide a reference basis for follow-up operators.
URI: http://hdl.handle.net/11455/98393
Rights: 同意授權瀏覽/列印電子全文服務,2022-01-25起公開。
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