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標題: High Mobilities in Layered InSe Transistors with Indium-Encapsulation-Induced Surface Charge Doping
作者: Li, Mengjiao
Lin, Che-Yi
Yang, Shih-Hsien
Chang, Yuan-Ming
Chang, Jen-Kuei
Yang, Feng-Shou
Zhong, Chaorong
Jian, Wen-Bin
Lien, Chen-Hsin
Ho, Ching-Hwa
Liu, Heng-Jui
Huang, Rong
Li, Wenwu
Lin, Yen-Fu
Chu, Junhao
關鍵字: 2D electronics;InSe transistors;logic circuits;low‐frequency noise;surface charge transfer doping
Project: Advanced materials (Deerfield Beach, Fla.), Volume 30, Issue 44, Page(s) e1803690.
Tunability and stability in the electrical properties of 2D semiconductors pave the way for their practical applications in logic devices. A robust layered indium selenide (InSe) field-effect transistor (FET) with superior controlled stability is demonstrated by depositing an indium (In) doping layer. The optimized InSe FETs deliver an unprecedented high electron mobility up to 3700 cm2 V-1 s-1 at room temperature, which can be retained with 60% after 1 month. Further insight into the evolution of the position of the Fermi level and the microscopic device structure with different In thicknesses demonstrates an enhanced electron-doping behavior at the In/InSe interface. Furthermore, the contact resistance is also improved through the In insertion between InSe and Au electrodes, which coincides with the analysis of the low-frequency noise. The carrier fluctuation is attributed to the dominance of the phonon scattering events, which agrees with the observation of the temperature-dependent mobility. Finally, the flexible functionalities of the logic-circuit applications, for instance, inverter and not-and (NAND)/not-or (NOR) gates, are determined with these surface-doping InSe FETs, which establish a paradigm for 2D-based materials to overcome the bottleneck in the development of electronic devices.
DOI: 10.1002/adma.201803690
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