Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/99285
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dc.contributor.authorChen, Kuan-Tingzh_TW
dc.contributor.authorQiu, Yu-Yanzh_TW
dc.contributor.authorTang, Mingzh_TW
dc.contributor.authorLee, Chia-Fengzh_TW
dc.contributor.authorDai, Yi-Luzh_TW
dc.contributor.authorLee, Min-Hungzh_TW
dc.contributor.authorChang, Shu-Tongzh_TW
dc.contributor.author張書通zh_TW
dc.date2018-
dc.date.accessioned2019-12-04T02:52:09Z-
dc.date.available2019-12-04T02:52:09Z-
dc.identifier.issn1533-4880zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/99285-
dc.description.abstractIn this paper, we investigate the negative-capacitance fin field-effect (NC-FinFET) and extend the design beyond the 7-nm technology node. A 7-nm-node NC-FinFET is presented using the Landau-Khalatnikov equation and the physical equations of a 3D technology computer-aided design simulation. We propose a new NC-FinFET with double ferroelectric hafnium zircon dioxide layers. This device exhibits noticeable voltage gains in the sub-threshold region, can decrease subthreshold swing (SS) effectively, has a wide-ranged uniform SS lower than 60 mV/dec, and can downscale the threshold voltage without increasing the off current. The static noise margin of the static random access memory using the new NC-FinFET is simulated and shows good performance with improved SS and threshold voltage.zh_TW
dc.language.isoenzh_TW
dc.relationJournal of nanoscience and nanotechnology, Volume 18, Issue 10, Page(s) 6873-6878.zh_TW
dc.titleNegative-Capacitance Fin Field-Effect Transistor Beyond the 7-nm Nodezh_TW
dc.typeJournal Articlezh_TW
dc.identifier.doi10.1166/jnn.2018.15725zh_TW
dc.awards2018zh_TW
item.grantfulltextrestricted-
item.fulltextwith fulltext-
item.cerifentitytypePublications-
item.languageiso639-1en-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeJournal Article-
Appears in Collections:電機工程學系所
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